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Journal of Computer Science and Technology 2009, Vol. 24 Issue (3) :405-417    DOI:
Distributed Computing and Systems Current Issue | Archive | Adv Search << | Next Articles >>
Taxonomy of Data Prefetching for Multicore Processors
Surendra Byna, Member, IEEE, Yong Chen (陈勇), Student Member, ACM, IEEE, and Xian-He Sun (孙贤和), Member, ACM, Senior Member, IEEE
Department of Computer Science, Illinois Institute of Technology, Chicago, Illinois 60616, U.S.A.

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Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream. While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.

Articles by authors
Surendra Byna
Yong Chen
Xian-He Sun
Keywordstaxonomy of prefetching strategies    multicore processors    data prefetching    memory hierarchy     
Received 2008-07-28; Revised 2009-05-05

This research was supported in part by the National Science Foundation of USA under Grant Nos. EIA-0224377, CNS-0406328, CNS-0509118, and CCF-0621435.

Cite this article:   
Surendra Byna, Yong Chen, and Xian-He Sun.Taxonomy of Data Prefetching for Multicore Processors[J]  Journal of Computer Science and Technology, 2009,V24(3): 405-417
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