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Journal of Computer Science and Technology 2016, Vol. 31 Issue (1) :77-106    DOI: 10.1007/s11390-016-1613-y
Computer Architectures and Systems Current Issue | Archive | Adv Search << Previous Articles | Next Articles >>
Modular Timing Constraints for Delay-Insensitive Systems
Hoon Park1,2, Anping He3*, Marly Roncken1, Xiaoyu Song2, and Ivan Sutherland1
1 Asynchronous Research Center, Portland State University, Portland, OR 97201, U.S.A.;
2 Department of Electrical and Computer Engineering, Portland State University, Portland, OR 97201, U.S.A.;
3 School of Information Science and Engineering, Lanzhou University, Lanzhou 730000, China

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Abstract This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component's gate-level circuit implementation obeys the component's handshake protocol specification. Because the handshake protocols are delay insensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component's constraints in any self-timed system built using the library. The library descriptions of a handshake component's circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.
Articles by authors
Hoon Park
Anping He
Marly Roncken
Xiaoyu Song
Ivan Sutherland
Keywordsself-timed circuit   delay-insensitive system   model checking   timing analysis   design pattern     
Received 2014-10-14;
Fund:

This work was supported by the National Natural Science Foundation of China under Grant No. 61402121.

Corresponding Authors: Anping He     Email: heap@lzu.edu.cn
About author: Hoon Park is a Ph.D. candidate in the Department of Electrical and Computer Engineering, Portland State University. Hoon was born in Seoul, Korea, and received his B.S. degree in mechanical engineering from Pukyong National University in 2004. He received his M.S. degree in electrical and computer engineering from Portland State University in 2007. He joined the Asynchronous Research Center in 2011 where he started focusing his research on verifying timing constraints for asynchronous circuits.
Cite this article:   
Hoon Park, Anping He, Marly Roncken, Xiaoyu Song, Ivan Sutherland.Modular Timing Constraints for Delay-Insensitive Systems[J]  Journal of Computer Science and Technology, 2016,V31(1): 77-106
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http://jcst.ict.ac.cn:8080/jcst/EN/10.1007/s11390-016-1613-y
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