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Journal of Computer Science and Technology 2016, Vol. 31 Issue (1) :124-136    DOI: 10.1007/s11390-016-1616-8
Computer Architectures and Systems Current Issue | Archive | Adv Search << Previous Articles | Next Articles >>
Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function
Ji-Liang Zhang1, Member, CCF, ACM, IEEE, Qiang Wu2, Yi-Peng Ding3 Yong-Qiang Lv4, Member, CCF, ACM, IEEE, Qiang Zhou4, Senior Member, CCF, ACM, IEEE Zhi-Hua Xia5, Xing-Ming Sun5, and Xing-Wei Wang1*
1 Software College, Northeastern University, Shenyang 110819, China;
2 College of Information Science and Engineering, Hunan University, Changsha 410082, China;
3 School of Physics and Electronics, Central South University, Changsha 410083, China;
4 Research Institute of Information Technology, Tsinghua University, Beijing 100084, China;
5 School of Computer and Software, Nanjing University of Information Science and Technology, Nanjing 210044, China

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Abstract Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.
Articles by authors
Ji-Liang Zhang
Qiang Wu
Yi-Peng Ding
Yong-Qiang Lv
Qiang Zhou
Zhi-Hua Xia
Xing-Ming Sun
Xing-Wei Wang
Keywordsphysical unclonable function (PUF)   FPGA   intellectual property protection   fabrication variation   hardware security     
Received 2014-03-29;

This work was supported in part by the National Science Foundation for Distinguished Young Scholars of China under Grant No. 61225012, the National Natural Science Foundation of China under Grant Nos. 61572123, 61501525, 61402162, 61232016, and U1405254, Hunan Province Science and Technology Project under Grant No. 2014RS4033, and the PAPD fund.

About author: Ji-Liang Zhang received his B.E. degree from Shandong University of Science and Technology, Qingdao, in 2009, and his Ph.D. degree in computer science and technology from Hunan University, Changsha, in 2015. In 2013~2014, he worked as a research scholar at the Maryland Embedded Systems and Hardware Security Lab, University of Maryland, College Park. He is currently an associate professor in the Software College, Northeastern University, Shenyang. His research interests include hardware security, IOT security, embedded system security, and software security.
Cite this article:   
Ji-Liang Zhang, Qiang Wu, Yi-Peng Ding, Yong-Qiang Lv, Qiang Zhou, Zhi-Hua Xia, Xing-Ming Sun, Xing-Wei Wang.Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function[J]  Journal of Computer Science and Technology, 2016,V31(1): 124-136
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