›› 2013,Vol. 28 ›› Issue (4): 682-688.doi: 10.1007/s11390-013-1368-7

所属专题: Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

一种健壮和高能效的65nm SOC物理实现方法

Bin Xiao1,2,3 (肖斌), Yi-Fu Zhang1,2,3 (张译夫), Yan-Ping Gao1,2,3 (高燕萍), Liang Yang3 (杨梁) Dong-Mei Wu1,3 (吴冬梅), and Bao-Xia Fan3 (范宝峡)   

  • 收稿日期:2012-09-28 修回日期:2013-03-07 出版日期:2013-07-05 发布日期:2013-07-05
  • 基金资助:

    This work is supported by the National Natural Science Foundation of China under Grant Nos. 61003064, 61050002, 61070025, 61100163, the National High Technology Research and Development 863 Program of China under Grant Nos. 2012AA010901, 2012AA011002, 2012AA012202, 2013AA014301.

A Robust and Power-Efficient SoC Implementation in 65nm

Bin Xiao1,2,3 (肖斌), Yi-Fu Zhang1,2,3 (张译夫), Yan-Ping Gao1,2,3 (高燕萍), Liang Yang3 (杨梁) Dong-Mei Wu1,3 (吴冬梅), and Bao-Xia Fan3 (范宝峡)   

  1. 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2. University of Chinese Academy of Sciences, Beijing 100049, China;
    3. Loongson Technology Corporation Limited, Beijing 100190, China
  • Received:2012-09-28 Revised:2013-03-07 Online:2013-07-05 Published:2013-07-05
  • Supported by:

    This work is supported by the National Natural Science Foundation of China under Grant Nos. 61003064, 61050002, 61070025, 61100163, the National High Technology Research and Development 863 Program of China under Grant Nos. 2012AA010901, 2012AA011002, 2012AA012202, 2013AA014301.

龙芯2H是龙芯系列处理器中的第一款高复杂度的SOC芯片.它的芯片面积为117mm2, 采用65nm CMOS LP/GP 工艺生产,共包含1.52亿晶体管.它集成了主频达到1GHz的龙芯处理器核和丰富的高速或低速的外部接口模块. 为了克服深亚微米工艺设计中的在片波动问题,在时钟生成与分布的过程中采用了许多新的设计方法,以及集成了各类的PVT测试电路由于硅后调试.为了满足芯片在不同应用场景中的低功耗设计要求,设计中采用了多种工业上常用的方法,比如动态频率和电压调节,电源门控技术以及多电压域设计.

Abstract: Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

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