›› 2013,Vol. 28 ›› Issue (1): 106-118.doi: 10.1007/s11390-013-1315-7

所属专题： Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

多核处理器中并行事务的资源快照模型

Lei Zhao (赵雷), Member, CCF, ACM, and Ji-Wen Yang (杨季文), Member, CCF, ACM   

  • 收稿日期:2011-06-01 修回日期:2012-08-20 出版日期:2013-01-05 发布日期:2013-01-05
  • 基金资助:

    This work is supported by the National Natural Science Foundation of China under Grant No. 61073061.

Resources Snapshot Model for Concurrent Transactions in Multi-Core Processors

Lei Zhao (赵雷), Member, CCF, ACM, and Ji-Wen Yang (杨季文), Member, CCF, ACM   

  1. School of Computer Science and Technology, Soochow University, Suzhou 215006, China
  • Received:2011-06-01 Revised:2012-08-20 Online:2013-01-05 Published:2013-01-05
  • Supported by:

    This work is supported by the National Natural Science Foundation of China under Grant No. 61073061.

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事务处理的并行性是数据库系统中提升事务处理性能的重要因素.事务存在两个层面的并行性：事务间并行性和事务内并行性.随着多核处理器的发展,事务处理并行性的改善出现了新的转机.事务执行的高效率来源于较低的依赖性.依赖性阻碍了并行性的提高.本文介绍了可同时应用于事务间并行性和事务内并行性研究的资源快照模型,提出了事务间调度的非重做算法和事务内调度的处理器分配算法.上述算法可大大提高由不同核数处理器构成的异构集群处理事务流的能力.

Abstract: Transaction parallelism in database systems is an attractive way of improving transaction performance. There exists two levels of transaction parallelism, inter-transaction level and intra-transaction level. With the advent of multicore processors, new hopes of improving transaction parallelism appear on the scene. The greatest execution efficiency of concurrent transactions comes from the lowest dependencies of them. However, the dependencies of concurrent transactions stand in the way of exploiting parallelism. In this paper, we present Resource Snapshot Model (RSM) for resource modeling in both levels. We propose a non-restarting scheduling algorithm in the inter-transaction level and a processor assignment algorithm in the intra-transaction level in terms of multi-core processors. Through these algorithms, execution performance of transaction streams will be improved in a parallel system with multiple heterogeneous processors that have different number of cores.

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