›› 2013,Vol. 28 ›› Issue (1): 119-128.doi: 10.1007/s11390-013-1316-6

所属专题： Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

电路级划分的三维片上多核系统中测试外壳扫描链的硅通孔数目最小化研究

Yuan-Qing Cheng1,2 (成元庆), Student Member, CCF, IEEE, Lei Zhang1 (张磊), Member, CCF, IEEE Yin-He Han1,* (韩银和), Member, CCF, ACM, IEEE, and Xiao-Wei Li1 (李晓维), Senior Member, CCF, IEEE   

  • 收稿日期:2012-07-03 修回日期:2012-10-03 出版日期:2013-01-05 发布日期:2013-01-05
  • 基金资助:

    This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.

TSV Minimization for Circuit — Partitioned 3D SoC Test Wrapper Design

Yuan-Qing Cheng1,2 (成元庆), Student Member, CCF, IEEE, Lei Zhang1 (张磊), Member, CCF, IEEE Yin-He Han1,* (韩银和), Member, CCF, ACM, IEEE, and Xiao-Wei Li1 (李晓维), Senior Member, CCF, IEEE   

  1. 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2. Graduate University of Chinese Academy of Sciences, Beijing 100049, China
  • Received:2012-07-03 Revised:2012-10-03 Online:2013-01-05 Published:2013-01-05
  • Supported by:

    This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.

PDF (PC)

2559

随着半导体制造工艺的不断进步而片上互连线延迟并未同步缩小,导致互连线延迟成为未来芯片集成的性能瓶颈.因而,三维集成电路技术被提出来作为延续摩尔定律的一种新方法.它利用硅通孔把不同的电路模块在垂直方向上互连起来,很好的解决了互连线延迟问题.由于三维集成电路自身独有的特性,有许多问题值得研究.本文重点研究电路级划分的三维片上多核系统IP核的测试外壳优化问题.首先, 我们使用2D SoC测试外壳的优化算法优化测试时间.然后,作为垂直互连线的硅通孔被用来连接测试壳扫描链,由于要通过绑定管脚进行绑定对齐,硅通孔要占用很大的面积,因而它也需要作为优化的目标之一.在本文中,我们提出一系列启发式算法,在不延长测试时间的情况下,减少测试外壳所用硅通孔的数目.该方法分为扫描链分配和功能输入/输出端口插入两个步骤,它们各自都可以显著减少硅通孔的数目.大量的实验数据分析表明,通过我们的方法设计的测试壳扫描链可以显著减少硅通孔的数目,即,与随机方法相比,可以减少60.5%,与直观方法相比可以减少26%.

Abstract: Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Threedimensional (3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias (TSVs) to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips (SoCs). Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically, i.e., as much as 60.5% reductions in comparison with the random method and 26% in comparison with the intuitive method.

[1] Davis J A, Venkatesan R, Kaloyeros A et al. Interconnectlimits on gigascale integration (GSI) in the 21st century. Proceedingsof the IEEE, 2001, 89(3): 305-324.
[2] Lewis D L, Lee H H S. Test circuit-partitioned 3D IC designs.In Proc. ISVLSI, May 2009, pp.139-144.
[3] Lee H-H S, Chakrabarty K. Test challenges for 3D integratedcircuits. IEEE Design & Test of Computers, 2009, 26(5):26-35.
[4] Marinissen E J. Test challenges for 3D-SICs: All the old, mostof the recent, and then some new! In Proc. ITC, Nov. 2009.
[5] Marinissen E J, Arendsen R, Bos G et al. A structuredand scalable mechanism for test access to embedded resuablecores. In Proc. ITC, Oct. 1998, pp.284-293.
[6] Iyengar V, Chakrabarty K, Marinissen E J. Wrapper/TAMco-optimization, constraint-driven test scheduling, and testerdata volume reduction for SOCs. In Proc. the 39th DAC,Jun. 2002, pp.685-690.
[7] Huang Y, Reddy S M, Cheng W T et al. Optimal core wrapperwidth selection and SOC test scheduling based on 3-D binpacking algorithm. In Proc. ITC, Oct. 2002, pp.74-82.
[8] Loi I, Mitra S, Lee T H, Fujita S, Benini L. A low-overheadfault tolerance scheme for TSV-based 3D network on chiplinks. In Proc. ICCAD, Nov. 2008, pp.598-602.
[9] Wu X, Falkenstern P, Xie Y. Scan chain design for threedimensionalintegrated circuits (3D ICs). In Proc. the 25thInt. Conf. Computer Design, Oct. 2007, pp.208-214.
[10] Chandran U, Zhao D. Thermal driven test access routing inhyper-interconnected three-dimensional system-on-chip. InProc. the 24th Int. Symp. Defect and Fault Tolerance inVLSI Systems, Oct. 2009, pp.410-418.
[11] Noia B, Charabarty K, Xie Y. Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. InProc. ICCD, Oct. 2009, pp.70-77.
[12] Iyengar V, Chakrabarty K, Marinissen E J. Test wrapper andtest access mechanism co-optimization for system-on-chip. InProc. ITC, Oct. 2001, pp.1023-1032.
[13] Marinissen E J, Goel S K, Lousberg M. Wrapper design forembedded core test. In Proc. ITC, Oct. 2000, pp.911-920.
[14] International technology roadmap for semiconductors.http://www.itrs.net/links/2009ITRS/Home2009.htm, July2012.
[15] Mak T M. Test challenges for 3D circuits. In Proc. the 12thIOLTS, Jul. 2006, p.79.
[16] Chen P Y, Wu C W, Kwai D M. On-chip TSV testing for 3DIC before bonding using sense amplification. In Proc. ATS,Nov. 2009, pp.450-455.
[17] Lewis D L, Lee H H S. Test strategies for 3D die-stacked integratedcircuits. In Proc. DATE, Apr. 2009.
[18] Lewis D L, Lee H H S. A scan-island based design enablingpre-bond testability in die-stacked microprocessors. In Proc.ITC, Oct. 2007, pp.1-8.
[19] Marinissen E J, Zorian Y. Testing 3D chips containingthrough-silicon vias. In Proc. ITC, Nov. 2009, pp.1-11.
[20] Wu X, Chen Y, Chakrabarty K, Xie Y. Test-access mechanismoptimization for core-based three-dimensional SOCs. InProc. ICCD, Oct. 2008, pp.212-218.
[21] Jiang L, Huang L, Xu Q. Test architecture design and optimizationfor three-dimensional SoCs. In Proc. DATE, Apr.2009, pp.220-225.
[22] Jiang L, Xu Q, Chakrabarty K, Mak T M. Layout-driventest-architecture design and optimization for 3D SoCs underprebond test-pin-count constraint. In Proc. ICCAD, Nov.2009, pp.191-196.
[23] Huang Y J, Li J F. Testability exploration of 3-D RAMs andCAMs. In Proc. ATS, Nov. 2009, pp.397-402.
[24] Zhao X, Lewis D L, Lee H H S, Lim S K. Pre-bond testablelow-power clock tree design for 3D stacked ICs. In Proc. ICCAD,Nov. 2009, pp.184-190.
[25] Roy S K, Ghosh S, Rahaman H, Giri C. Test wrapper designfor 3D system-on-chip using optimized number of TSVs. InProc. ISED, Dec. 2010, pp.197-202.
No related articles found!
Viewed
Full text


Abstract

Cited
  Shared   
  Discussed   
No Suggested Reading articles found!
版权所有 © 《计算机科学技术学报》编辑部
本系统由北京玛格泰克科技发展有限公司设计开发 技术支持：support@magtech.com.cn
总访问量：