›› 2013,Vol. 28 ›› Issue (1): 14-27.doi: 10.1007/s11390-013-1309-5

所属专题: Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇


Zhi-Guang Chen (陈志广), Nong Xiao* (肖侬), Member, IEEE, Fang Liu (刘芳), Member, CCF and Yi-Mo Du (杜溢墨)   

  • 收稿日期:2011-12-31 修回日期:2012-08-29 出版日期:2013-01-05 发布日期:2013-01-05
  • 基金资助:

    Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2013AA013201, the National Natural Science Foundation of China under Grant Nos. 61025009, 61232003, 61120106005, 61170288.

Reorder Write Sequence by Hetero-Buffer to Extend SSD's Lifespan

Zhi-Guang Chen (陈志广), Nong Xiao* (肖侬), Member, IEEE, Fang Liu (刘芳), Member, CCF and Yi-Mo Du (杜溢墨)   

  1. State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha 410073, China
  • Received:2011-12-31 Revised:2012-08-29 Online:2013-01-05 Published:2013-01-05
  • Supported by:

    Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2013AA013201, the National Natural Science Foundation of China under Grant Nos. 61025009, 61232003, 61120106005, 61170288.


Abstract: The limited lifespan is the Achilles' heel of solid state drives (SSDs) based on NAND flash. NAND flash has two drawbacks that degrade SSDs' lifespan. One is the out-of-place update. Another is the sequential write constraint within a block. SSDs usually employ write buffer to extend their lifetime. However, existing write buffer schemes only pay attention to the first drawback, while neglect the second one. We propose a hetero-buffer architecture covering both aspects simultaneously. The hetero-buffer consists of two components, dynamic random access memory (DRAM) and the reorder area. DRAM endeavors to reduce write traffic as much as possible by pursuing a higher hit ratio (overcome the first drawback). The reorder area focuses on reordering write sequence (overcome the second drawback). Our hetero-buffer outperforms traditional write buffers because of two reasons. First, the DRAM can adopt existing superior cache replacement policy, thus achieves higher hit ratio. Second, the hetero-buffer reorders the write sequence, which has not been exploited by traditional write buffers. Besides the optimizations mentioned above, our hetero-buffer considers the work environment of write buffer, which is also neglected by traditional write buffers. By this way, the hetero-buffer is further improved. The performance is evaluated via trace-driven simulations. Experimental results show that, SSDs employing the hetero-buffer survive longer lifespan on most workloads.

[1] Kang S, Park S, Jung H, Shim H, Cha J. Performance trade-offs in using NVRAM write buffer for flash memory-basedstorage devices. IEEE Transactions on Computers, 2009,58(6): 744-758.
[2] Hu J, Jiang H, Tian L, Xu L. PUD-LRU: An erase-efficientwrite buffer management algorithm for flash memory SSD.In Proc. the 18th Annual IEEE/ACM International Sympo-sium on Modeling, Analysis and Simulation of Computer andTelecommunication Systems, Aug. 2010, pp.69-78.
[3] Wu G, Eckart B, He X. BPAC: An adaptive write buffer mana-gement scheme for flash-based solid state drives. In Proc. the26th Symposium on Mass Storage Systems and Technologies,May 2010, pp.1-6.
[4] Kim H, Ahn S. BPLRU: A buffer management scheme forimproving random writes in flash storage. In Proc. the 6thUSENIX Conference on File and Storage Technologies, Feb.2008, pp.239-252.
[5] Jo H, Kang J U, Park S Y, Kim J S, Lee J. FAB: Flash-awarebuffer management policy for portable media players. IEEETransactions on Consumer Electronics, 2006, 52(2): 485-493.
[6] Sun G, Joo Y, Chen Y, Niu D, Xie Y, Chen Y, Li H. Ahybrid solid-state storage architecture for the performance,energy consumption, and lifetime improvement. In Proc. the16th International Conference on High-Performance Com-puter Architecture, Jan. 2010, pp.1-12.
[7] Soundararajan G, Prabhakaran V, Balakrishnan M, WobberT. Extending SSD lifetimes with disk-based write caches. InProc. the 8th USENIX Conference on File and Storage Tech-nologies, Feb. 2010, pp.101-114.
[8] Hu X Y, Eleftheriou E, Haas R, Iliadis I, Pletka R. Write am-plification analysis in flash-based solid state drives. In Proc.the Israeli Experimental Systems Conference 2009, May 2009,Article No.10.
[9] Park S Y, Jung D, Kang J U, Kim J S, Lee J. CFLRU: A re-placement algorithm for flash memory. In Proc. the 2006 In-ternational Conference on Compilers, Architecture, and Syn-thesis for Embedded Systems, Oct. 2006, pp.234-241.
[10] Lee S, Park D, Chung T, Lee D, Park S, Song H. A logbuffer based flash translation layer using fully associative sec-tor translation. ACM Transactions on Embedded ComputingSystems, 2007, 6(3): 18.
[11] Johnson T, Shasha D. 2Q: A low overhead high performancebuffer management replacement algorithm. In Proc. the 20thInternational Conference on Very Large Data Bases, Sept.1994, pp.439-450.
[12] Megiddo N, Modha D S. ARC: A self-tuning, low overhead re-placement cache. In Proc. the Conference on File and Stor-age Technologies, Mar. 31-Apr. 2, 2003, pp.115-130.
[13] Jiang S, Zhang X D. LIRS: An efficient low inter-referencerecency set replacement policy to improve buffer cache per-formance. In Proc. the International Conference on Mea-surements and Modeling of Computer Systems, Jun. 2002,pp.31-42.
[14] Narayanan D, Donnelly A, Rowstron A. Write off-loading:Practical power management for enterprise storage. ACMTransactions on Storage (TOS), 2008, 4(3): 10.
[15] Gupta A, Kim Y, Urgaonkar B. DFTL: A flash translationlayer employing demand-based selective caching of page-leveladdress mappings. In Proc. the 14th International Confer-ence on Architectural Support for Programming Languagesand Operating Systems, Mar. 2009, pp.229-240.
[16] Xiao N, Chen Z G, Liu F, LaiMC, An L F. P3Stor: A parallel,durable flash-based SSD for enterprise-scale storage systems.Science China Information Science, 2011, 54(6): 1129-1141.
[17] Park D, Debnath B, Du D. CFTL: A convertible flash trans-lation layer with consideration of data access patterns. InProc. the 2010 International Conference on Measurementand Modeling of Computer Systems, Jun. 2010, pp.365-366.
No related articles found!
Full text



[1] 谢立; 陈珮珮; 杨培根; 孙钟秀;. The Design and Implementation of an OA System ZGL1[J]. , 1988, 3(1): 75 -80 .
[2] 许志明;. Discrete Interpolation Surface[J]. , 1990, 5(4): 329 -332 .
[3] 张钹; 张铃;. On Memory Capacity of the Probabilistic Logic Neuron Network[J]. , 1993, 8(3): 62 -66 .
[4] 招兆铿; 戴军; 陈文丹;. Automated Theorem Proving in Temporal Logic:T-Resolution[J]. , 1994, 9(1): 53 -62 .
[5] . 颜色图像滤波的四元数扩散方法[J]. , 2006, 21(1): 126 -136 .
[6] . [J]. 计算机科学技术学报, 0, (): 1 .
[7] Chuan Shi (石川), Member, CCF, IEEE, Zhen-Yu Yan (闫震宇), Member, IEEE. 一种基于事后决策的社团发现算法[J]. , 2011, 26(5): 792 -805 .
[8] Su-Ke Li (李素科), Zhi Guan (关志), Li-Yong Tang (唐礼勇), and Zhong Chen (陈钟), Member, . 利用消费者评论对产品特征排序[J]. , 2012, 27(3): 635 -649 .
[9] Rui Li, Ke-Bin Liu, Xiangyang Li, Yuan He, Wei Xi, Zhi Wang, Ji-Zhong Zhao, Meng Wan. 无线传感网诊断方法的评估:概念与分析[J]. , 2014, 29(5): 887 -900 .
[10] Guo-Jie Li. Preface[J]. , 2015, 30(2): 225 -226 .
版权所有 © 《计算机科学技术学报》编辑部
本系统由北京玛格泰克科技发展有限公司设计开发 技术支持:support@magtech.com.cn