›› 2013,Vol. 28 ›› Issue (1): 14-27.doi: 10.1007/s11390-013-1309-5

所属专题: Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

用异构缓冲对写请求重排序以延长SSD的寿命

Zhi-Guang Chen (陈志广), Nong Xiao* (肖侬), Member, IEEE, Fang Liu (刘芳), Member, CCF and Yi-Mo Du (杜溢墨)   

  • 收稿日期:2011-12-31 修回日期:2012-08-29 出版日期:2013-01-05 发布日期:2013-01-05
  • 基金资助:

    Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2013AA013201, the National Natural Science Foundation of China under Grant Nos. 61025009, 61232003, 61120106005, 61170288.

Reorder Write Sequence by Hetero-Buffer to Extend SSD's Lifespan

Zhi-Guang Chen (陈志广), Nong Xiao* (肖侬), Member, IEEE, Fang Liu (刘芳), Member, CCF and Yi-Mo Du (杜溢墨)   

  1. State Key Laboratory of High Performance Computing, National University of Defense Technology, Changsha 410073, China
  • Received:2011-12-31 Revised:2012-08-29 Online:2013-01-05 Published:2013-01-05
  • Supported by:

    Supported by the National High Technology Research and Development 863 Program of China under Grant No. 2013AA013201, the National Natural Science Foundation of China under Grant Nos. 61025009, 61232003, 61120106005, 61170288.

寿命有限是基于NAND闪存的SSD的一大缺陷.NAND闪存的两个特性降低了SSD的寿命,一个是非定点更新,另一个是同一物理块内的顺序写约束.SSD通常采用写缓冲延长寿命.但是,现有的写缓冲策略一般只关注以上提到的第一个特性,第二个特性被忽略.本文提出一种异构的写缓冲,同时兼顾以上两点.该异构写缓冲由两部分组成,DRAM和重排序区域.其中,DRAM主要用来取得较高的命中率,以克服第一个缺陷;冲排序区域主要用来对写请求冲排序,以克服第二个缺陷.该异构缓冲从两方面优于传统的写缓冲.首先,DRAM可以采用现有的任何好性能缓存替换策略,可以取得较高的命中率;其次,该缓冲对写请求冲排序,这是传统的写缓冲没有涉及到的.除了以上提到的优化,我们还考虑了SSD写缓冲的工作环境.使该异构写缓冲的性能得到进一步的提升.模拟实验证明,对于大多数工作负载,本文提出的异构写缓冲显然优于传统的写缓冲.

Abstract: The limited lifespan is the Achilles' heel of solid state drives (SSDs) based on NAND flash. NAND flash has two drawbacks that degrade SSDs' lifespan. One is the out-of-place update. Another is the sequential write constraint within a block. SSDs usually employ write buffer to extend their lifetime. However, existing write buffer schemes only pay attention to the first drawback, while neglect the second one. We propose a hetero-buffer architecture covering both aspects simultaneously. The hetero-buffer consists of two components, dynamic random access memory (DRAM) and the reorder area. DRAM endeavors to reduce write traffic as much as possible by pursuing a higher hit ratio (overcome the first drawback). The reorder area focuses on reordering write sequence (overcome the second drawback). Our hetero-buffer outperforms traditional write buffers because of two reasons. First, the DRAM can adopt existing superior cache replacement policy, thus achieves higher hit ratio. Second, the hetero-buffer reorders the write sequence, which has not been exploited by traditional write buffers. Besides the optimizations mentioned above, our hetero-buffer considers the work environment of write buffer, which is also neglected by traditional write buffers. By this way, the hetero-buffer is further improved. The performance is evaluated via trace-driven simulations. Experimental results show that, SSDs employing the hetero-buffer survive longer lifespan on most workloads.

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