›› 2013,Vol. 28 ›› Issue (6): 1025-1044.doi: 10.1007/s11390-013-1395-4

所属专题： Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

一种时序的位置感知页面映射的闪存转换层

Youngjae Kim1, Aayush Gupta2, and Bhuvan Urgaonkar3, Senior Member, ACM, IEEE   

  • 收稿日期:2013-01-03 修回日期:2013-05-16 出版日期:2013-11-05 发布日期:2013-11-05
  • 作者简介:Youngjae Kim is a computer science R&D staff member for the National Center for Computational Sciences at Oak Ridge National Laboratory, USA. He received the Ph.D. degree in computer science and engineering from the Department of Computer Science and Engineering of the Pennsylvania State University, USA, in 2009. His research interests include operating systems, parallel I/O and file systems, and storage systems.

A Temporal Locality-Aware Page-Mapped Flash Translation Layer

Youngjae Kim1, Aayush Gupta2, and Bhuvan Urgaonkar3, Senior Member, ACM, IEEE   

  1. 1 National Center for Computational Sciences, Oak Ridge National Laboratory, Oak Ridge, TN 37831, U.S.A.;
    2 IBM Almaden Research Center, San Jose, CA 95120, U.S.A.;
    3 Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, U.S.A.
  • Received:2013-01-03 Revised:2013-05-16 Online:2013-11-05 Published:2013-11-05
  • Supported by:

    This research was funded in part by the Natural Science Foundation of U.S. under Grant Nos. CCF-0811670, CNS-0720456, a gift from Cisco System, Inc. and partially through the Office of Science of the U.S. Department of Energy under Contract No. DE-AC05-00OR22725.

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在企业规模环境下更好地利用闪存,必须处理随机写性能差的问题。我们分析了性能差的重要原因之一:闪存转换层(FTL)的设计,以实现虚拟到物理的地址转换并隐藏闪存的写前擦除特点。我们提出了一种完整的核心FTL引擎设计的模式转换,提出了一种基于需求的闪存转换层(DFTL)。DFTL能选择性地缓存页面层地址匹配。基于一种闪存仿真框架FlashSim,我们在实际企业规模工作负载下的实验评价证明了DFTL在企业规模存储系统中的可用性:改进了性能;减少了垃圾收集工作量;相对目前最流行的实现方式:混合FTL模式,提供了更好的超负载行为。例如:从一个在大规模金融所的OLTP应用的显著地随机写主导的I/O轨迹,显示了平均反应时间相对混合FTL模式的78%的改进(源于垃圾收集器操作的3折缩减)。即便对于著名的读主导的TPC-H基准,DFTL虽然引入了额外的负担, 仍然改进了56%的反应时间。有趣的是,当基于DFTL的SSD上的写回缓存被使用,DFTL甚至优于基于页面的FTL模式,在金融轨迹中改进了72%的反应时间。

Abstract: The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the flash translation layer (FTL) which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer (DFTL) which selectively caches pagelevel address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: 1) improved performance, 2) reduced garbage collection overhead and 3) better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.

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