›› 2014,Vol. 29 ›› Issue (4): 656-663.doi: 10.1007/s11390-014-1457-2

所属专题： Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

优于最坏情况设计：发展与机遇

Jason Cong1 (丛京生), Fellow, ACM, IEEE, Henry Duwe2, Rakesh Kumar2, Member, ACM, IEEE, and Sen Li1 (李森)   

  1. 1. Computer Science Department, University of California, Los Angeles, CA 90095-1596, U.S.A.;
    2. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801, U.S.A.
  • 出版日期:2014-07-05 发布日期:2014-07-05
  • 作者简介:Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the Computer Science Department of University of California, Los Angeles, UCLA, the director of Center for Domain-Specific Computing (CDSC), co-director of UCLA/Peking University Joint Research Institute in Science and Engineering, and co-director of the VLSI CAD Laboratory.
  • 基金资助:

    The research is partially supported by the National Science Foundation of USA under Grant No. CCF-0903541.

Better-Than-Worst-Case Design：Progress and Opportunities

Jason Cong1 (丛京生), Fellow, ACM, IEEE, Henry Duwe2, Rakesh Kumar2, Member, ACM, IEEE, and Sen Li1 (李森)   

  1. 1. Computer Science Department, University of California, Los Angeles, CA 90095-1596, U.S.A.;
    2. Electrical and Computer Engineering Department, University of Illinois at Urbana-Champaign, Urbana, IL 61801, U.S.A.
  • Online:2014-07-05 Published:2014-07-05
  • About author:Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor's Professor at the Computer Science Department of University of California, Los Angeles, UCLA, the director of Center for Domain-Specific Computing (CDSC), co-director of UCLA/Peking University Joint Research Institute in Science and Engineering, and co-director of the VLSI CAD Laboratory.
  • Supported by:

    The research is partially supported by the National Science Foundation of USA under Grant No. CCF-0903541.

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由于当代集成电路设计更小的特征尺寸以及制造变动， 设计者们不得不为由此导致的更强变动性预留出更大的余量，而这需要以降低性能和增加功率要求为代价。优于最坏情况设计与最坏情况设计相比，可以同时解决变动性问题和获得更高的性能/能源效率。本文调研了此领域的最新进展，概述了最有代表性的工作，探讨了优于最坏情况设计的未来研究方向。

Abstract: Today, designers are forced to reduce performance and increase power requirements in order to reserve larger margins that are required due to the greater variability introduced by smaller feature sizes and manufacturing variations of modern IC designs. The better-than-worst-case design can both address the variability problem and achieve higher performance/energy efficiency than the worst-case design. This paper surveys the progress to date, provides a snapshot of the most representative methods in this field, and discusses the future research directions of the better-than-worst-case design.

[1] Cong J, Minkovich K. Logic synthesis for better than worstcase designs. In Proc. Int. Symp. VLSI Design, Automation and Test, April 2009, pp.166-169.

[2] Cong J, Minkovich K. Mapping for better than worst-case delays in LUT-based FPGA designs. In Proc. the 16th FPGA, Feb. 2008, pp.56-64.

[3] Austin T, Bertacco V, Blaauw D, Mudge T. Opportunities and challenges for better than worst-case design. In Proc. ASP-DAC, Jan. 2005, pp.2-7.

[4] Ernst D, Kim N S, Das S et al. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. the 36th MICRO, Dec. 2003, pp.7-18.

[5] Liu Y, Ye R, Yuan F et al. On logic synthesis for timing speculation. In Proc. ICCAD, Nov. 2012, pp.591-596.

[6] Kahng A B, Kang S, Kumar R, Sartori J. Recovery-driven design: A power minimization methodology for error-tolerant processor modules. In Proc. the 47th DAC, June 2010, pp.825-830.

[7] Kahng A, Kang S, Kumar R, Sartori J. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In Proc. the 16th HPCA, June 2010.

[8] Narayanan S, Sartori J, Kumar R, Jones D. Scalable stochastic processors. In Proc. DATE, Mar. 2010, pp.335-338.

[9] Lingamneni A, Enz C, Nagel J L et al. Energy parsimonious circuit design through probabilistic pruning. In Proc. DATE, Mar. 2011.

[10] Ye R, Wang T, Yuan F et al. On reconfiguration-oriented approximate adder design and its application. In Proc. ICCAD, Nov. 2013, pp.48-54.

[11] Tosson A, Garg S, Anis M. Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. In Proc. the 21st VLSI-SoC, Oct. 2013, pp.368-373.

[12] Ganapathy S, Canal R, Gonzalez A, Rubio A. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. In Proc. DATE, Mar. 2010, pp.417-422.

[13] Wan L, Chen D. DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proc. ICCAD, Nov. 2009, pp.172-179.

[14] Chan W T, Kahng A B, Kang S et al. Statistical analysis and modeling for error composition in approximate computation circuits. In Proc. the 31st ICCD, Oct. 2013, pp.47-53.

[15] Kahng A, Kang S, Kumar R et al. Slack redistribution for graceful degradation under voltage overscaling. In Proc. the 15th ASP-DAC, Jan. 2010, pp.825-831.

[16] Abdallah R, Lee Y H, Shanbhag N R. Timing error statistics for energy-efficient robust DSP systems. In Proc. DATE, Mar. 2011.

[17] Sloan J, Kesler D, Kumar R, Rahimi A. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. In Proc. DSN, July 2010, pp.161-170.

[18] Deka B, Birklykke A, Duwe H et al. Markov chain algorithms: A template for building future robust low power systems. In Proc. Asilomar Conf. Signals, Systems and Computers, Nov. 2013, pp.118-125.

[19] Kesler D, Deka B, Kumar R. A hardware acceleration technique for gradient descent and conjugate gradient. In Proc. the 9th SASP, June 2011, pp.94-101.

[20] Sartori J, Kumar R. Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applications. IEEE Transactions on Multimedia, 2013, 15(2): 279290.

[21] Cong J, Gururaj K. Assuring application-level correctness against soft errors. In Proc. ICCAD, Nov. 2011, pp.150-157.

[22] Cong J, Ghodrat M A, Gill M et al. Architecture support for accelerator-rich CMPs. In Proc. the 49th DAC, June 2012, pp.843-849.

[23] Cong J, Ghodrat M A, Gill M. CHARM: A composable heterogeneous accelerator-rich microprocessor. In Proc. ISLPED, July 30-August 1, 2012, pp.379-384.

[24] Cong J, Ercegovac M, Huang M et al. Energy-efficient computing using adaptive table lookup based on nonvolatile memories. In Proc. ISLPED, Sept. 2013, pp.280-285.
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[1] 刘明业; 洪恩宇;. Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems[J]. , 1986, 1(2): 83 -92 .
[2] 陈世华;. On the Structure of (Weak) Inverses of an (Weakly) Invertible Finite Automaton[J]. , 1986, 1(3): 92 -100 .
[3] 高庆狮; 张祥; 杨树范; 陈树清;. Vector Computer 757[J]. , 1986, 1(3): 1 -14 .
[4] 陈肇雄; 高庆狮;. A Substitution Based Model for the Implementation of PROLOG——The Design and Implementation of LPROLOG[J]. , 1986, 1(4): 17 -26 .
[5] 黄河燕;. A Parallel Implementation Model of HPARLOG[J]. , 1986, 1(4): 27 -38 .
[6] 闵应骅; 韩智德;. A Built-in Test Pattern Generator[J]. , 1986, 1(4): 62 -74 .
[7] 唐同诰; 招兆铿;. Stack Method in Program Semantics[J]. , 1987, 2(1): 51 -63 .
[8] 闵应骅;. Easy Test Generation PLAs[J]. , 1987, 2(1): 72 -80 .
[9] 朱鸿;. Some Mathematical Properties of the Functional Programming Language FP[J]. , 1987, 2(3): 202 -216 .
[10] 李明慧;. CAD System of Microprogrammed Digital Systems[J]. , 1987, 2(3): 226 -235 .
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