›› 2015,Vol. 30 ›› Issue (1): 84-96.doi: 10.1007/s11390-015-1506-5

所属专题： Computer Architecture and Systems

• Special Section on Selected Paper from NPC 2011 • 上一篇    下一篇

一种基于交叉开关的大数据互联架构

Chao Wang1(王超), Member, CCF, ACM, IEEE, Xi Li1,2(李曦), Senior Member, CCF, Member, ACM, IEEE, Xue-Hai Zhou1(周学海), Senior Member, CCF, Member, ACM, IEEE   

  1. 1 School of Computer Science, University of Science and Technology of China, Hefei 230027, China;
    2 School of Software Engineering, University of Science and Technology of China, Suzhou 215123, China
  • 收稿日期:2014-07-15 修回日期:2014-12-12 出版日期:2015-01-05 发布日期:2015-01-05
  • 作者简介:Chao Wang received his B.S. and Ph.D. degrees from University of Science and Technology of China, Hefei, in 2006 and 2011 respectively, both in computer science. He is an associate processor with School of Computer Science, University of Science and Technology of China, Hefei. His research interests focus on multicore and reconfigurable computing. He has authored more than 60 publications and patents. He is now an editor board member of MICPRO, IET CDT, IJHPSA and IJBPIM. He serves as the publicity chair of HiPEAC 2015 and ISPA 2014, and the guest editor for TCBB and IJPP. He is a member of CCF, ACM, and IEEE.
  • 基金资助:

    This work was supported by the National Natural Science Foundation of China under Grant Nos. 61379040, 61272131, 61202053, 61222204, and 61221062, the Natural Science Foundation of Jiangsu Province of China under Grant No. SBK201240198, the Fundamental Research Funds for the Central Universities of China under Grant No. WK0110000034, the Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (CAS) under Grant No. CARCH201407, and the Strategic Priority Research Program of CAS under Grant No. XDA06010403.

CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data

Chao Wang1(王超), Member, CCF, ACM, IEEE, Xi Li1,2(李曦), Senior Member, CCF, Member, ACM, IEEE, Xue-Hai Zhou1(周学海), Senior Member, CCF, Member, ACM, IEEE   

  1. 1 School of Computer Science, University of Science and Technology of China, Hefei 230027, China;
    2 School of Software Engineering, University of Science and Technology of China, Suzhou 215123, China
  • Received:2014-07-15 Revised:2014-12-12 Online:2015-01-05 Published:2015-01-05
  • About author:Chao Wang received his B.S. and Ph.D. degrees from University of Science and Technology of China, Hefei, in 2006 and 2011 respectively, both in computer science. He is an associate processor with School of Computer Science, University of Science and Technology of China, Hefei. His research interests focus on multicore and reconfigurable computing. He has authored more than 60 publications and patents. He is now an editor board member of MICPRO, IET CDT, IJHPSA and IJBPIM. He serves as the publicity chair of HiPEAC 2015 and ISPA 2014, and the guest editor for TCBB and IJPP. He is a member of CCF, ACM, and IEEE.
  • Supported by:

    This work was supported by the National Natural Science Foundation of China under Grant Nos. 61379040, 61272131, 61202053, 61222204, and 61221062, the Natural Science Foundation of Jiangsu Province of China under Grant No. SBK201240198, the Fundamental Research Funds for the Central Universities of China under Grant No. WK0110000034, the Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (CAS) under Grant No. CARCH201407, and the Strategic Priority Research Program of CAS under Grant No. XDA06010403.

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片上互联架构给大数据时代的片上多核处理器设计方法带来了严峻的挑战.就目前的发展趋势来看,在构建基于FPGA的异构多核片上系统时,基于交叉开关的互联架构依然是一种相对比较高效可行的解决方案.本文提出了一种基于交叉开关的片上互联策略CRAIS,主要针对片上的微处理器以及可重构的知识产权IP核之间的互联.CRAIS允许数据通路针对应用程序的运行时特征实现自动配置和动态重构.本文基于FPGA设计并实现了原型系统.实验数据表明,相对于目前在FPGA上常用的另外一种架构StarNet,CRAIS能够提升到7倍的性能加速,同时只占用StarNet的21%~35%的硬件资源.

Abstract: On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip interconnection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the state-of-the-art StarNet approach, while it only utilizes 21%~35% hardware resources of StarNet.

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