计算机科学技术学报 ›› 2021,Vol. 36 ›› Issue (1): 33-43.doi: 10.1007/s11390-020-0741-6

所属专题： Computer Architecture and Systems

• • 上一篇    下一篇

以主存为中心的ARMv8众核体系结构性能评估:以飞腾2000+为例

Jian-Bin Fang, Member, CCF, Xiang-Ke Liao, Fellow, CCF, Chun Huang, and De-Zun Dong*   

  1. College of Computer, National University of Defense Technology, Changsha 410073, China
  • 收稿日期:2020-06-24 修回日期:2020-12-09 出版日期:2021-01-05 发布日期:2021-01-23
  • 通讯作者: De-Zun Dong E-mail:dongg@nudt.edu.cn
  • 作者简介:Jian-Bin Fang is an assistant professor in computer science at National University of Defense Technology (NUDT), Changsha. He obtained his Ph.D. degree in computer science from Delft University of Technology in 2014. His research interests include parallel programming for many-cores, parallel compilers, performance modeling, and scalable algorithms. He is a member of CCF.
  • 基金资助:
    This work is partially funded by the National Key Research and Development Program of China under Grant No. 2018YFB0204301, and the National Natural Science Foundation of China under Grant Nos. 61972408 and 61602501.

Performance Evaluation of Memory-Centric ARMv8 Many-Core Architectures: A Case Study with Phytium 2000+

Jian-Bin Fang, Member, CCF, Xiang-Ke Liao, Fellow, CCF, Chun Huang, and De-Zun Dong*        

  1. College of Computer, National University of Defense Technology, Changsha 410073, China
  • Received:2020-06-24 Revised:2020-12-09 Online:2021-01-05 Published:2021-01-23
  • Contact: De-Zun Dong E-mail:dongg@nudt.edu.cn
  • About author:Jian-Bin Fang is an assistant professor in computer science at National University of Defense Technology (NUDT), Changsha. He obtained his Ph.D. degree in computer science from Delft University of Technology in 2014. His research interests include parallel programming for many-cores, parallel compilers, performance modeling, and scalable algorithms. He is a member of CCF.
  • Supported by:
    This work is partially funded by the National Key Research and Development Program of China under Grant No. 2018YFB0204301, and the National Natural Science Foundation of China under Grant Nos. 61972408 and 61602501.

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1、研究背景(context)
高性能计算领域已经明显地转向众核体系结构设计。其中,基于ARMv8的众核处理器是构建未来高性能计算机系统的典型代表。这个趋势可以从将64核的飞腾2000+处理器用于构建天河三号原型机系统和将48核的A64FX处理器用于构建富岳超算系统中看出。因此,有必要在这类体系结构上评估典型高性能计算应用核心的性能表现。
2、目的(Objective) 在ARMv8众核处理器上评估典型高性能计算应用核心的性能表现将不仅有利于挖掘该类处理器的计算潜能,还将为进一步优化体系结构设计提供参考。
3、方法(Method)以飞腾2000+处理器为例,本文着重评测该处理器的缓存和主存子系统,结合roofline模型分析影响高性能计算应用性能的体系结构特征。
4、结果(Result & Findings) 通过使用微基准测试的方法,系统地测量了飞腾2000+处理器的访存延迟与带宽性能;通过对飞腾2000+处理器实例化Roofline模型,可视化该处理器的计算与访存间的平衡性,直观地展示不同应用在该处理器上的性能瓶颈;通过优化两个典型的应用核心,发现飞腾2000+能够取得良好的性能表现。
5、结论(Conclusions) 评测结果显示基于ARMv8的众核处理器能够在多个典型高性能计算应用核心上取得良好的性能,得益于其计算与访存的平衡设计。此外,对于类似于GEMM的应用核心,共享的L2缓存设计是进一步提升性能的瓶颈,建议未来设计私有的L2缓存以优化体系结构设计。

关键词: 众核处理器体系结构, 以主存为中心的设计, 性能评估

Abstract: This article presents a comprehensive performance evaluation of Phytium 2000+, an ARMv8-based 64-core architecture. We focus on the cache and memory subsystems, analyzing the characteristics that impact the high-performance computing applications. We provide insights into the memory-relevant performance behaviours of the Phytium 2000+ system through micro-benchmarking. With the help of the well-known roofline model, we analyze the Phytium 2000+ system, taking both memory accesses and computations into account. Based on the knowledge gained from these micro-benchmarks, we evaluate two applications and use them to assess the capabilities of the Phytium 2000+ system. The results show that the ARMv8-based many-core system is capable of delivering high performance for a wide range of scientific kernels.

Key words: many-core architecture, memory-centric design, performance evaluation

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