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Recursive Implementation of VLSI Circuits
冯玉琳;
1986,1(2 ):72 -82.
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2448
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This is an introduction for Escher——the geometrical layout system.An Escher circuit description is a hierarchical structure composed of cells,wires,connectors between wires,and pins that connect wires to cells.Cells may correspond to primitive circuit elements,or they may be defined in terms of lower level subcells.Unlike other geometrical layout systems,a subcell may be instance of the cell being defined.When such a recursive cell definition is instantiated,the recursion is unwound in a manner reminiscent …
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An Effective Test Generation Algorithm for Combinational Circuits
王建潮; 魏道政;
1986,1(4 ):1 -16.
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2517
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1217
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In this paper,an analysis of backtrack behavior in PODEM(the test generation algorithmfor combinational circuits presented by P.Goel)is given.It is pointed out that there are stillmany unnecessary backtracks in PODEM on some occasions.A new test generation algorithmnamed IPODEM is therefore proposed in this paper.IPODEM is an improvement over PODEMwith emphasis on backtrack of decision tree.A new backtrack approach is developed in thisalgorithm.It is shown that only O(j)of backtrack consumption is needed in...
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Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits
魏道政;
1990,5(2 ):156 -163.
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2592
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1156
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Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to the parallel critical path tracing for functional block-level combinational circuits.If the word length of the host computer is m,then the parallel critical path tracing will be approximately m times faster than the original one.
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Testability Analysis at Switch Level for CMOS Circuits
沈理;
1990,5(2 ):197 -202.
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2597
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1168
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In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexity of the algorithm is nearly linear.
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A Complete Critical Path Algorithm for Test Generation of Combinational Circuits
周权; 魏道政;
1991,6(1 ):74 -82.
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2571
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1226
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It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.
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The Researches in Fault-Tolerant D ataflow Architecture
王镭; 谭英;
1991,6(4 ):395 -398.
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2269
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1357
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Fault-tolerant dataflow system is an entirely new field.This paper presents an overview of FTDF-TD.a fault-tolerant dataflow system.Various aspects of FTDF-TD,such as the architecture, the fault-tolerant strategy,and its reliability,are described.The research on overhead and performance evaluation based on software simulation is introduced.It is shown that FTDF-TD gets valuable results in reducing overhead,execution time and increasing reliability of processor array,compared with two other fault-tolerant sy…
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Pseudo-Random Test Generation for Large Combinational Circuits
李忠诚; 闵应骅;
1992,7(1 ):19 -28.
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2276
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1129
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In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The l…
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A Multiple-Valued Algebra for Modeling MOS VLSI Circuits at Switch-Level
胡谋;
1992,7(2 ):175 -184.
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2375
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1271
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A multiple-valued algebra for modeling MOS VLSI circuits at switch-level is proposed in this paper. Its structure and properties are studied.This algebra can be used to transform a MOS digital circuit to a switch-level algebraic expression so as to generate the truth table for the circuit and to derive a Boolean expression for it.In the paper,methods to construct a switch-level algebraic expression for a circuit and methods to simplify expressions are given.This algebra provides a new tool for MOS VLSI circ…
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Optimizing FORTRAN Programs for Hierarchical Memory Parallel Processing Systems
金国华; 陈福接;
1993,8(3 ):19 -30.
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3012
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1290
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Parallel loops account for the greatest amount of parallelism in numerical programs.Executing nested loops in parallel with low run-time overhead is thus very important for achieving high perform- ance in parallel processing systems.However,in parallel processing systems with caches or local memo- ries in memory hierarchies,“thrashing problem”may arise whenever data move back and forth between the caches or local memories in different processors. Previous techniques can only deal with the rather simple case…
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Optimized Parallel Execution of Declarative Programs on Distributed Memory Multiprocessors
沈美明; 田新民; 王鼎兴; 郑纬民; 温冬婵;
1993,8(3 ):43 -52.
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2819
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1232
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In this paper,we focus on the compiling implementation of parallel logic language PARLOG and functional language ML on distributed memory multiprocessors.Under the graph rewriting framework, a Heterogeneous Parallel Graph Rewriting Execution Model(HPGREM)is presented firstly.Then based on HPGREM,a parallel abstract machine PAM/TGR is described.Furthermore,several optimizing compilation schemes for executing declarative programs on transputer array are proposed. The performance statistics on a transputer arr…
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Parallel Execution of Prolog on Shared-Memory Multiprocessors
高耀清; 王鼎兴; 郑纬民; 沈美明; 黄志毅; 胡守仁; Giorgio Levi;
1993,8(4 ):43 -50.
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2781
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Logic programs offer many opportunities for the exploitation of parallelism.But the parallel execution of a task incurs various overheads This paper focuses on the issues relevant to parallelizing Prolog on shared-memory multiprocessors efficiently.
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On the Problem of Optimizing Parallel Programs for Complex Memory Hierarchies
金国华; 陈福接
1994,9(1 ):1 -26.
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2657
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1088
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Based on a thorough study of the relationship between array element accesses and loop indices of the nested loop, a method is presented with which the staggering relation and the compacting relation between the threads of the nested loop (either with a single linear function or with multiple linear functions) can be determined at compile-time,and accordingly the nested loop (either perfectly nested one or imperfectly nested one)can be restructured to avoid the thrashing problem. Due to its simplicity, our m…
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TSP: A Heterogeneous Multiprocessor Supercomputing System Based on i860XP
黄国勇; 李三立;
1994,9(3 ):285 -288.
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2991
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Numerous new RISC processors provide support for supercomputing. By using the "mini-Cray" i860 superscalar processor, an add-on board has been developed to boost the performance of a real time system. A parallel heterogeneous multiprocessor supercomputing system, TSP, is constructed. In this paper, we present the system design consideration and described the architecture of the TSP and its features.
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Adaptive Memory Coherence Algorithms in DSVM
周建强; 谢立; 戴非; 孙钟秀;
1994,9(4 ):365 -372.
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3165
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Based on the characteristics of distrubuted system and the behavior of parallelprograms, this paper presents the fixed and randofored competitive memory coherence algorithms for distributed shared virtual memory These algorithms exploit parallel programs' locality of reference and dribit good competitive property Our simulation shows that the fixed and randomized algorithms achieve better performance and higher stability than other strategies such as write-invalldate and write-update.
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A General Architecture Model of CPDL Interpreter
徐福培; 罗驰; 金亚东;
1995,10(5 ):463 -469.
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3075
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1362
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This paper puts forward'a general architecture model of CPDL Interpreter,profiles the logical structure of the modules, and analyses the burden distri-bution among the interpreter units. The work has significance in developing practical interpreter products.
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Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits
陈偕雄;
1995,10(6 ):564 -568.
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2864
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1423
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An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.
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Hybridity in Embedded Computing Systems
虞慧群; 孙永强;
1996,11(1 ):90 -96.
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3256
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1465
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An embedded system is a system that computer is used as a componelit ina larger device. In this paper, we study hybridity in embedded systems andpresent an interval based temporal logic to express and reason about hybridproperties of such ldnd of systems.
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Design Technique of I~2L Circuits Based on Multi-Valued Logic
吴训威; 杭国强;
1996,11(2 ):181 -187.
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2915
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1426
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This paper proposes the use of the current signal to express logic values and establishes the theory of grounded current switches suitable for I2L circuits.Based on the advantage that current signals are easy to be added, the design technique of I2L circuits by means of the multi-valued current signal is proposed.It is shown that simpler structure of I2L circuits can be obtained with this technique.
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Global Register Allocation for SIMD Multiprocessors
BenjaminHAO; DavidPEARSON; RichardZIPPEL;
1996,11(3 ):222 -236.
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2851
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1309
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It is relatively clear how to map regular, repetitive or grid oriented computations onto SIMD architectures. It is not so clear, however, how to do this for irregular computations even though there may be significant amounts of intrinsic parallelism in branch free code. We study compilation techniques for this type of code when targeted to SIMD computers and illustrate their use on a simple model architecture.In this paper, we present one of the compilation techniques, global mpister allocation,we have deve…
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A Comparative Analysis of Different Arbitration Protocols for Multiple-Bus Multiprocessors
庄旗铭; 蒋定安; 杨庆;
1996,11(3 ):313 -325.
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2802
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1330
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Earlier performance studies of multiple-bus multiprocessor systetns assume a ran-dom selection of competing requests for bus assignment and ignore the effects of realistic bus arbitration schemes on the performance of such systetns. In this paper, we present performance analysis of the multiple-bus systems with different arbitration protocols.The priority protocols considered are random selection, fixed priority, rotating priority, roundrobin and FIFO. Analytica1 models are developed for each of these five …
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Embedding Binary Tree in VLSI/WSI Processor Array
陈宗汉;
1996,11(3 ):326 -336.
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2627
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1190
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Many reconfiguration schemes for fault-tolerant binary tree architectures have been proposed in the lite..t.re[1-6]. The VLSI layouts of most previous studies are based on the classical H-tree layout, resulting in low area utilization and likely an unnecessarily high manufacturing cost simply due to the waste of a significaot portion of silicon area. In this paper, we present an area-efficient approach to the reconfigurable binary tree architecture. Area utilization and interconnection complexity of our des…
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NONH:A New Cache-Based Coherence Protocol for Linked List Structure DSM System and Its Performance Evaluation
房至一; 鞠九滨;
1996,11(4 ):405 -415.
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3421
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（464KB）（
1256
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The management of memory coherence is an important problem in distributed shared memory (DSM) system. In a cache-based coherence DSM system using linked list structure, the key to maintaining the coherence and improving system performance is how to manage the owner in the linked list. This paper presents the design of a new management protocol-NONH (New-OwnerNew-Head) and its performance evaluation. The analysis results show that thisprotocol can improve the scalability and performence of a coherent DSM sys…
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The Methodology of Testability Prediction for Sequential Circuits
徐拾义; 陈斯;
1996,11(6 ):529 -541.
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3018
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1409
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Increasingly, test generation algorithms are being developed with the con-tinuous creations of incredibly sophisticated computing systems. Of all the developments of testable as well as reliable designs for computing systems, the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue. Although dozens of algorithms have been proposed to cope with this issue, it still remains much to be desired in solving such problems as to d…
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A Neural Network Appraoch to Fault Diagnosis in Analog Circuits
尉乃红; 杨士元; 童诗白;
1996,11(6 ):542 -550.
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3404
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1386
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This paper presents a neural network based fault diagnosis approach for analog circuits, taking the tolerances of circuit elements into account. Specifi-cally, a normalization rule of input information, a pseudo-fault domain border (PFDB) pattern selection method and a new output error function are proposed for training the backpropagation (BP) network to be a fault diagnoser. Experi-mental results demonstrate that the diagnoser performs as well as or better than any classical approaches in terms of accurac…
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DYNAMEM-A Microarchitecture for Improving Memory Disambiguation at Run-Time
王显著; 廖恒; 李三立;
1996,11(6 ):589 -600.
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2946
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1288
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This paper presents a new microarchitecture technique named DYNAMEM,in which memory reference instructions are dynamically scheduled and can be executed out-of-order. Load instructions can bypass store instructions specula-tively, even if the store instructions'addresses are unknown. DYNAMEM can greatly alleviate the restraints of ambiguous memory dependencies. Simulation results show that the frequency of false load is low. Mechanism has been pro-vided to repair false loads with low penalty, and to achieve…
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Scheduling PVM Tasks
鞠九滨; 王勇; 尹玉;
1997,12(2 ):167 -176.
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3061
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1316
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This paper describes a PVM task scheduler designed and implemented by the authors. The scheduler supports selecting idle workstations, scheduling pool tasks and dynamically produced subtasks. It can improve resource utilization,reduce job response time and simplify programming.
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A Multiagent Dynamic interaction Testbed:Theoretic Framework, System Architecture and Experimentation
王学军; 石纯一;
1997,12(2 ):121 -132.
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2840
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1552
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Recent research on Distributed Artificial Intelligence (DAI) has focused upon agellts' interaction in Multiagent Systems. This paper presents a text understanding oriented multiagent dynamic illteraction testbed (TUMIT): the theoretic framework based upon game theory, the free-market-like system architecture, and experimentation on TUMIT. Unlike other DAI testbeds, TUMIT views different text understanding (TU) methods as different "computational resources", and makes agents Choose different TU paths and com…
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A Lock-Based Cache Coherence Protocol for Scope Consistency
胡伟武; 施巍松; 唐志敏; 李明;
1998,13(2 ):97 -109.
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3269
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2356
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Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being used in very large scale multiprocessors with tens of thousands of nodes. This paper proposes a lock-based cache coherence protocol for scope conyistency. It does not rely on directory information to maintain cache coherence. Instead, cache coherence is mailltained through requiring the releasin…
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A Framework of Memory Consistency Models
胡伟武; 施巍松; 唐志敏;
1998,13(2 ):110 -124.
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3401
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1343
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Previous descriptions of memory consistency models in shared-memory multiprocessor systems are mainly expressed as constraints on the memory access event ordering and hence are hardwae-centric. This paper presents a framework of memory consistency models which describes the memory consistency model on the behavior level.Based on the understanding that the behavior of an execution is determined by the execution order of confiicting accesses, a memory consistency model is defined as an interprocessor synchro…
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Out-of-Order Execution in Sequentially Consistent Shared-Memory Systems:Theory and Experiments
胡伟武; 夏培肃;
1998,13(2 ):125 -140.
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3562
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1750
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Thaditional implementation of sequential consistency in shared-memory systems requires memory accesses to be globally performed in program order. Based on an event ordering model for correct executions in shared-memory systems, this paper proposes and proves that out-of-order execution does not influence the correctness of an execution providing certain condition is met. Simulation results show that out-of-order execution proposed in this paper is an effective way to improve the performance of a sequentiall…
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On Dependability of Computing Systems
徐拾义;
1999,14(2 ):116 -128.
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3051
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1335
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With the rapid development and wide applicatioos of computing systems on which more reliance hu been put, a dependable syatem will be much more important than ever. This paper is hrst aimed at giving informal but precise definitions characterizing the various attributes of dependability of computing sys- tems and then the importance of (and the relationshipa among) all the attributes are explained . Dependability is first introduced as a global concept which subsumes the usual attributea of reliability, ava…
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Reference Implementation of Scalable I/O Low-Level API on Intel Paragon
孙凝晖;
1999,14(3 ):206 -223.
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3183
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1366
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The Scalable I/O (SIO) Initiative's Low-Level Application Pro- gramming Interface (SIO LLAPI)provides file system implementers with a simplelow-Level interface to support high-level parallel I/O interfaces efficiently and ef fectively. This paper describes a reference implementation and the evaluation of the SIO LLAPI on the Intel Paragon multicomputer. The implementation provides the file system structure and striping algorithm compatible with the Parallel File System (PFS) of Intel Paragon, and runs eithe…
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Orthogonal Drawings of Graphs for the Automation of VLSI Circuit Design
刘彦佩;
1999,14(5 ):447 -459.
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3083
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1397
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This article shows the recent developments on orthogonal draw-ings of graphs which have applications for the automation of VLSI circuit design.Meanwhile, a number of problems are posed for further research.
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Bounded Algebra and Current-Mode Digital Circuits
吴训威;
1999,14(6 ):551 -557.
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3118
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1386
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This paper proposes two bounded arithmetic operations, which areeasily realized with current signals. Based on these two operations, a bounded algebra system suitable for describing current-mode digital circuits is developed andits relationship with the Boolean algebra, which is suitable for representing voltagemode digital circuits, is investigated. Design procedure for current-mode circuitsusing the proposed algebra system is demonstrated on a number of common circuit elements which are used to realize ar…
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Optimum Tactics of Parallel Multi-Grid Algorithm with Virtual Boundary Forecast Method Running on a Local Network with the PVM Platform
郭庆平; Yakup Paker; 章社生; Dennis Parkinson; 卫加宁;
2000,15(4 ):355 -359.
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3164
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In this paper, an optimum tactic of multi-grid parallel algorithmwith virtual boundary forecast method is disscussed, and a two-stage implementationis presented. The numerical results of solving a non-linear heat transfer equationshow that the optimum implementation is much better than the non-optimum one.
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Forecasting the Efficiency of Test Generation Algorithms for Combinational Circuits
徐拾义; Tukwasibwe Justaf Frank;
2000,15(4 ):326 -337.
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3454
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1414
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In this era of VLSI circuits, testability is truly a very crucial issue.To generate a test set for a given circuit, choice of an algorithm from a number ofexisting test generation algorithms to apply is bound to vary from circuit to circuit.In this paper, the Genetic Algorithm is used in order to construct an accurate modelfor some existing test generation algorithms that are being used everywhere in theworld. Some objective quantitative measures are used as an effective tool in makingsuch choice. Such meas…
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Forecasting the Efficiency of Test Generation Algorithms for Combinational Circuits
XU Shiyi（徐拾义）and Tukwasibwe Justaf Frank
2000,15(4 ):0 -0.
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2267
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1660
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Optimum Tactics of Parallel Multi-Grid Algorithm with Virtual Boundary Forecast Method Running on a Local Network with the PVM Platform
GUO Qingping（郭庆平），Yakup Paker，ZHANG Shesheng（章社生），Dennis Parkinson and WEI Jianing（卫佳宁）
2000,15(4 ):0 -0.
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2046
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1287
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A Novel Computer Architecture to Prevent Destruction by Viruses
GAO Qingshi（高庆狮），HU Yue（胡月），LI Lei（李磊），CHEN Xu（陈绪）
2002,17(3 ):0 -0.
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