›› 2011, Vol. 26 ›› Issue (4): 578-587.doi: 10.1007/s11390-011-1158-z

Special Issue: Surveys; Computer Architecture and Systems

• Special Section on Perspectives on Future Computer Science • Previous Articles     Next Articles

New Methodologies for Parallel Architecture

Dong-Rui Fan (范东睿), Member, CCF,IEEE, Xiao-Wei Li (李晓维), and Guo-Jie Li (李国杰), Fellow, CCF   

  1. Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China
  • Received:2011-05-03 Online:2011-07-05 Published:2011-07-05
  • Supported by:

    This work is in part supported by the National Basic Research 973 Program of China under Grant Nos. 2011CB302500, 2005CB321600, and the National Natural Science Foundation of China under Grant No.60921002.

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and para-llelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. Computers, etc.

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[32] Hu W, Chen Y. GS464V: A high-performance low-power XPU with512-bit vector extension. In Proc. Symp. High Performance Chips,Aug.22-24, Stanford University, USA, 2010.
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