›› 2012, Vol. 27 ›› Issue (1): 75-91.doi: 10.1007/s11390-012-1207-2

Special Issue: Computer Architecture and Systems

• Architecture and VLSI Design • Previous Articles     Next Articles

Efficient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers

Benjamín Sahelices1, Agustín de Dios1, Pablo Ibáñez2, Member, IEEE, Víctor Viñals-Yúfera2, Member, ACM, IEEE, and José María Llabería3   

  1. 1. Computer Science Department and HiPEAC European Network of Excellence, University of Valladolid, Valladolid, Spain;
    2. Computer Science and Systems Engineering Department, I3A Research Institute and HiPEAC European Network of Excellence, University of Zaragoza, Zaragoza, Spain;
    3. Computer Architecture Department and HiPEAC European Network of Excellence, Polytechnic University of Cataluña Barcelona, Spain
  • Received:2010-10-30 Revised:2011-08-23 Online:2012-01-05 Published:2012-01-05
  • Supported by:

    This work was supported in part by Spanish Government and European ERDF under Grant Nos. TIN2007-66423, TIN2010-21291-C02-01 and TIN2007-60625, gaZ: T48 research group (Aragón Government and European ESF), Consolider CSD2007-00050 (Spanish Government) and HiPEAC-2 NoE (European FP7/ICT 217068)

Synchronization in parallel programs is a major performance bottleneck in multiprocessor systems. Shared data is protected by locks and a lot of time is spent on the competition arising at the lock hand-off. In order to be serialized, requests to the same cache line can either be bounced (NACKed) or buffered in the coherence controller. In this paper, we focus mainly on systems whose coherence controllers buffer requests. In a lock hand-off, a burst of requests to the same line arrive at the coherence controller. During lock hand-off only the requests from the winning processor contribute to progress of the computation, since the winning processor is the only one that will advance the work. This key observation leads us to propose a hardware mechanism we call request bypassing, which allows requests from the winning processor to bypass the requests buffered in the coherence controller keeping the lock line. We present an inexpensive implementation of request bypassing that reduces the time spent on all the execution phases of a critical section (acquiring the lock, accessing shared data, and releasing the lock) and which, as a consequence, speeds up the whole parallel computation. This mechanism requires neither compiler or programmer support nor ISA or coherence protocol changes. By simulating a 32-processor system, we show that using request bypassing does not degrade but rather improves performance in three applications with low synchronization rates, while in those having a large amount of synchronization activity (the remaining four), we see reductions in execution time and in lock stall time ranging from 14% to 39% and from 52% to 71%, respectively. We compare request bypassing with a previously proposed technique called read combining and with a system that bounces requests, observing a significantly lower execution time with the bypassing scheme. Finally, we analyze the sensitivity of our results to some key hardware and software parameters.

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