›› 2013, Vol. 28 ›› Issue (4): 671-681.doi: 10.1007/s11390-013-1367-8

Special Issue: Computer Architecture and Systems

• Architecture and VLSI Design • Previous Articles     Next Articles

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

Ning Xu1 (徐宁), Senior Member, CCF, Yu-Chun Ma2,3,* (马昱春), Jia Liu1,2 (刘佳) and Shou-Chun Tao1,2 (陶守春)   

  1. 1. School of Computer Science and Technology, Wuhan University of Technology, Wuhan 430070, China;
    2. Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China;
    3. Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China
  • Received:2012-07-16 Revised:2013-02-07 Online:2013-07-05 Published:2013-07-05
  • Supported by:

    This work is supported by the National Natural Science Foundation of China under Grant No. 61076035 and TNList Cross-discipline Foundation of Tsinghua University, China.

To reduce the interconnect delay and improve the chip performance, three-dimensional (3D) chip emerged with the rapid increasing of chip integration and chip power density. Therefore, thermal issue is one of the critical challenges in 3D IC design due to the high power density. Multiple Supply Voltages (MSV) technique provides an efficient way to optimize power consumption which in turn may alleviate the hotspots. But the voltage assignment is limited not only by the performance constraints of the design, but also by the physical layout of circuit modules since the modules with the same voltage should be gathered to reduce the power-network routing resource. Especially in 3D designs, the optimization using MSV technique becomes even more complicated since the high temperature also influences the power consumption and delay on paths. In this paper, we address the voltage-island generation problem for MSV designs in 3D ICs based on a mixed integer linear programming (MILP) model. First, we propose a general MILP formulation for voltage-island generation to optimize thermal distribution as well as power-network routing resources while maintaining the whole chip performance. With the thermal-power interdependency, an iterative optimization approach is proposed to obtain the convergence. Experimental results show that our thermal-aware voltage-island generation approach can reduce the maximal on-chip temperature by 23.64% with a reasonable runtime and save the power-network routing resources by 16.71%.

[1] Hua H, Mineo C, Schoenfliess K, Sule A, Melamed S, JenkalR, Davis W R. Exploring compromises among timing, powerand temperature in three-dimensional integrated circuits. InProc. the 43th Design Automation Conference, June 2006,pp.997-1002.

[2] Hu J, Shin Y, Dhanwada N, Marculescu R. Architectingvoltage-islands in core based system-on-a-chip designs. InProc. Int. Symp. Low Power Electronics and Design, August2004, pp.180-185.

[3] Hung W, Link G, Xie Y, Vijaykrishnan N, Dhanwadaf N,Conner J. Temperature-aware voltage islands architecting insystem-on-chip design. In Proc. IEEE International Confer-ence on Computer Design, October 2005, pp.689-696.

[4] Mak W K, Chen J W. Voltage island generation under per-formance requirement for SoC designs. In Proc. Asia andSouth Pacific Design Automation Conference, January 2007,pp.798-803.

[5] Lee W P, Liu H Y, Chang Y W. Voltage island aware floor-planning for power and timing optimization. In Proc. Inter-national Conference on Computer-Aided Design, November2006, pp.389-394.

[6] Lee W P, Liu H Y, Chang Y W. An ILP algorithm for post-floorplanning votage-island generation considering power-network planning. In Proc. International Conference onComputer-Aided Design, November 2007, pp.650-655.

[7] Ma Y C, Qiu X, He X Q, Hong X L. Incremental power opti-mization for multiple supply voltage design. In Proc. Inter-national Symposium on Quality of Electronic Design, March2009, pp.280-286.

[8] Yu S A, Huang P Y, Lee Y M. A multiple supply voltage basedpower reduction method in 3-D ICs considering process vari-ations and thermal effects. In Proc. Asia and South PacificDesign Automation Conference, January 2009, pp.55-60.

[9] Cong J, Wei J, Zhang Y. A thermal-driven floorplanning al-gorithm for 3D ICs. In Proc. International Conference onComputer-Aided Design, November 2004, pp.306-313.

[10] Hung W L, Link G M, Xie Y, Vijaykrishnan N, Irwin M J.Interconnect and thermal-aware floorplanning for 3D micro-processors. In Proc. the 7th International Symposium onQuality Electronic Design, March 2006, pp.98-104.

[11] Yu H, Ho J, He L. Allocating power ground vias in 3D ICsfor simultaneous power and thermal integrity. ACM Trans-actions on Design Automation of Electronic Systems (TO-DAES), 2009, 14(3): Article No. 41.

[12] Yu H, Shi Y, He L, Karnik T. Thermal via allocation for3D ICs considering temporally and spatially variant thermalpower. IEEE Transactions on Very Large Scale IntegrationSystems (TVLSI), 2008, 16(12): 1609-1619.

[13] Wilkerson P, Raman A, Turowski M. Fast, automated thermalsimulation of three-dimensional integrated circuits. In Proc.the 9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena in Electronic Systems, June 2004,pp.706-713.

[14] Cong J, Zhang Y. Thermal via planning for 3-D ICs. InProc. International Conference on Computer-Aided Design,November 2005, pp.745-752.

[15] Cong J, Zhang Y. Thermal-driven multilevel routing for 3-DICs. In Proc. Asia and South Pacific Design AutomationConference, January 2005, pp.121-126.

[16] Cheng Y, Tsai C, Teng C, Kang S. Electrothermal Analysisof VLSI Systems. Springer, 2000.

[17] Ma Y C, Li X, Wang Y, Hong X L. Thermal-aware incre-mental floorplanning for 3D ICs based on MILP formulation.IEICE Transactions on Fundamentals of Electronics, Com-munications and Computer Sciences, 2009, E92-A(12): 2979-2989.
No related articles found!
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
[1] Liu Mingye; Hong Enyu;. Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems[J]. , 1986, 1(2): 83 -92 .
[2] Chen Shihua;. On the Structure of (Weak) Inverses of an (Weakly) Invertible Finite Automaton[J]. , 1986, 1(3): 92 -100 .
[3] Gao Qingshi; Zhang Xiang; Yang Shufan; Chen Shuqing;. Vector Computer 757[J]. , 1986, 1(3): 1 -14 .
[4] Chen Zhaoxiong; Gao Qingshi;. A Substitution Based Model for the Implementation of PROLOG——The Design and Implementation of LPROLOG[J]. , 1986, 1(4): 17 -26 .
[5] Huang Heyan;. A Parallel Implementation Model of HPARLOG[J]. , 1986, 1(4): 27 -38 .
[6] Min Yinghua; Han Zhide;. A Built-in Test Pattern Generator[J]. , 1986, 1(4): 62 -74 .
[7] Tang Tonggao; Zhao Zhaokeng;. Stack Method in Program Semantics[J]. , 1987, 2(1): 51 -63 .
[8] Min Yinghua;. Easy Test Generation PLAs[J]. , 1987, 2(1): 72 -80 .
[9] Zhu Hong;. Some Mathematical Properties of the Functional Programming Language FP[J]. , 1987, 2(3): 202 -216 .
[10] Li Minghui;. CAD System of Microprogrammed Digital Systems[J]. , 1987, 2(3): 226 -235 .

ISSN 1000-9000(Print)

         1860-4749(Online)
CN 11-2296/TP

Home
Editorial Board
Author Guidelines
Subscription
Journal of Computer Science and Technology
Institute of Computing Technology, Chinese Academy of Sciences
P.O. Box 2704, Beijing 100190 P.R. China
Tel.:86-10-62610746
E-mail: jcst@ict.ac.cn
 
  Copyright ©2015 JCST, All Rights Reserved