|  Cong J, Minkovich K. Logic synthesis for better than worstcase designs. In Proc. Int. Symp. VLSI Design, Automation and Test, April 2009, pp.166-169. Cong J, Minkovich K. Mapping for better than worst-case delays in LUT-based FPGA designs. In Proc. the 16th FPGA, Feb. 2008, pp.56-64. Austin T, Bertacco V, Blaauw D, Mudge T. Opportunities and challenges for better than worst-case design. In Proc. ASP-DAC, Jan. 2005, pp.2-7. Ernst D, Kim N S, Das S et al. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. the 36th MICRO, Dec. 2003, pp.7-18. Liu Y, Ye R, Yuan F et al. On logic synthesis for timing speculation. In Proc. ICCAD, Nov. 2012, pp.591-596. Kahng A B, Kang S, Kumar R, Sartori J. Recovery-driven design: A power minimization methodology for error-tolerant processor modules. In Proc. the 47th DAC, June 2010, pp.825-830. Kahng A, Kang S, Kumar R, Sartori J. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In Proc. the 16th HPCA, June 2010. Narayanan S, Sartori J, Kumar R, Jones D. Scalable stochastic processors. In Proc. DATE, Mar. 2010, pp.335-338. Lingamneni A, Enz C, Nagel J L et al. Energy parsimonious circuit design through probabilistic pruning. In Proc. DATE, Mar. 2011. Ye R, Wang T, Yuan F et al. On reconfiguration-oriented approximate adder design and its application. In Proc. ICCAD, Nov. 2013, pp.48-54. Tosson A, Garg S, Anis M. Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. In Proc. the 21st VLSI-SoC, Oct. 2013, pp.368-373. Ganapathy S, Canal R, Gonzalez A, Rubio A. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. In Proc. DATE, Mar. 2010, pp.417-422. Wan L, Chen D. DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proc. ICCAD, Nov. 2009, pp.172-179. Chan W T, Kahng A B, Kang S et al. Statistical analysis and modeling for error composition in approximate computation circuits. In Proc. the 31st ICCD, Oct. 2013, pp.47-53. Kahng A, Kang S, Kumar R et al. Slack redistribution for graceful degradation under voltage overscaling. In Proc. the 15th ASP-DAC, Jan. 2010, pp.825-831. Abdallah R, Lee Y H, Shanbhag N R. Timing error statistics for energy-efficient robust DSP systems. In Proc. DATE, Mar. 2011. Sloan J, Kesler D, Kumar R, Rahimi A. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. In Proc. DSN, July 2010, pp.161-170. Deka B, Birklykke A, Duwe H et al. Markov chain algorithms: A template for building future robust low power systems. In Proc. Asilomar Conf. Signals, Systems and Computers, Nov. 2013, pp.118-125. Kesler D, Deka B, Kumar R. A hardware acceleration technique for gradient descent and conjugate gradient. In Proc. the 9th SASP, June 2011, pp.94-101. Sartori J, Kumar R. Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applications. IEEE Transactions on Multimedia, 2013, 15(2): 279290. Cong J, Gururaj K. Assuring application-level correctness against soft errors. In Proc. ICCAD, Nov. 2011, pp.150-157. Cong J, Ghodrat M A, Gill M et al. Architecture support for accelerator-rich CMPs. In Proc. the 49th DAC, June 2012, pp.843-849. Cong J, Ghodrat M A, Gill M. CHARM: A composable heterogeneous accelerator-rich microprocessor. In Proc. ISLPED, July 30-August 1, 2012, pp.379-384. Cong J, Ercegovac M, Huang M et al. Energy-efficient computing using adaptive table lookup based on nonvolatile memories. In Proc. ISLPED, Sept. 2013, pp.280-285.