›› 2015, Vol. 30 ›› Issue (1): 84-96.doi: 10.1007/s11390-015-1506-5

Special Issue: Computer Architecture and Systems

• Special Section on Computer Architecture and Systems for Big Data • Previous Articles     Next Articles

CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data

Chao Wang1(王超), Member, CCF, ACM, IEEE, Xi Li1,2(李曦), Senior Member, CCF, Member, ACM, IEEE, Xue-Hai Zhou1(周学海), Senior Member, CCF, Member, ACM, IEEE   

  1. 1 School of Computer Science, University of Science and Technology of China, Hefei 230027, China;
    2 School of Software Engineering, University of Science and Technology of China, Suzhou 215123, China
  • Received:2014-07-15 Revised:2014-12-12 Online:2015-01-05 Published:2015-01-05
  • About author:Chao Wang received his B.S. and Ph.D. degrees from University of Science and Technology of China, Hefei, in 2006 and 2011 respectively, both in computer science. He is an associate processor with School of Computer Science, University of Science and Technology of China, Hefei. His research interests focus on multicore and reconfigurable computing. He has authored more than 60 publications and patents. He is now an editor board member of MICPRO, IET CDT, IJHPSA and IJBPIM. He serves as the publicity chair of HiPEAC 2015 and ISPA 2014, and the guest editor for TCBB and IJPP. He is a member of CCF, ACM, and IEEE.
  • Supported by:

    This work was supported by the National Natural Science Foundation of China under Grant Nos. 61379040, 61272131, 61202053, 61222204, and 61221062, the Natural Science Foundation of Jiangsu Province of China under Grant No. SBK201240198, the Fundamental Research Funds for the Central Universities of China under Grant No. WK0110000034, the Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (CAS) under Grant No. CARCH201407, and the Strategic Priority Research Program of CAS under Grant No. XDA06010403.

On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip interconnection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the state-of-the-art StarNet approach, while it only utilizes 21%~35% hardware resources of StarNet.

[1] Howe D, Costanzo M, Fey P et al. Big data: The future of biocuration. Nature, 2008, 455:47-50.

[2] Singh S. Computing without processors. Communications of ACM, 2011, 54(8):46-54.

[3] Huang Y, Ienne P, Temam O et al. Elastic CGRAs. In Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, February 2013, pp.171-180.

[4] Chen T, Du Z, Sun N et al. DianNao: A small-footprint high-throughput accelerator for ubiquitous machine learning. In Proc. the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, March 2014, pp.269-284.

[5] Chen Y, Luo T, Liu S et al. DaDianNao: A machinelearning supercomputer. In Proc. the 47th IEEE/ACM International Symposium on Microarchitecture, December 2014.

[6] Wang C, Li X, Chen P et al. Heterogeneous cloud framework for big data genome sequencing. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2014. (preprint)

[7] Wawrzynek J, Patterson D, Oskin M et al. RAMP: Research accelerator for multiple processors. IEEE Micro, 2007, 27(2):46-57.

[8] Panainte E, Bertels K, Vassiliadis S. The Molen compiler for reconfigurable processors. ACM Transactions on Embedded Computing Systems, 2007, 6(1): Article No. 6.

[9] Benini L, De Micheli G. Networks on chips: A new SoC paradigm. IEEE Computer, 2002, 35(1):70-78.

[10] Wolf W, Jerraya A, Martin G. Multiprocessor systemonchip (MPSoC) technology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(10):1701-1713.

[11] Dally W J, Towles B. Route, packets, not wires: On-chip interconnection networks. In Proc. the 38th Annual Design Automation Conference. June 2001, pp.684-689.

[12] Tuan V, Katsura N, Matsutani H et al. Evaluation of a multicore reconfigurable architecture with variable core sizes. In Proc. IEEE International Symposium on Parallel & Distributed Processing, May 2009.

[13] Tuan V M, Amano H. A mapping method for multi-process execution on dynamically reconfigurable processors. In Proc. the International Conference on Field-Programmable Technology, December 2007, pp.357-360.

[14] Liu S, Chen T, Li L et al. FreeRider: Non-local adaptive network-on-chip routing with packet-carried propagation of congestion information. IEEE Transactions on Parallel and Distributed Systems, 2014. (to be appeared).

[15] Schleupen K, Lelaich S, Mannion R et al. Dynamic partial FPGA reconfiguration in a prototype microprocessor system. In Proc. the International Conference on Field Programmable Logic and Applications, August 2007, pp.533-(\d)36.

[16] Kistler M, Perrone M, Petrini F. Cell multiprocessor communication network: Built for speed. IEEE Micro, 2006, 26(3):10-23.

[17] Hoskote Y, Vangal S, Singh A et al. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro, 2007, 27(5):51-(\d)1.

[18] Samuelsson H, Kumar S. Ring road NoC architecture. In Proc. Norchip Conference, November 2004, pp.16-19.

[19] Kwark J W, Jhon C S. Torus ring: Improving performance of interconnection network by modifying hierarchical ring. Parallel Computing, 2007, 33(1):2-20.

[20] Bourduas S, Zilic Z. A hybrid ring/mesh interconnect for network-on-chip using hierarchical rings for global routing. In Proc. the 1st International Symposium on Networks-onChip, May 2007, pp.195-204.

[21] Madsen J, Stidsen T, Kjaerulf P et al. Multi-objective design space exploration of embedded system platforms. In Proc. the IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems, October 2006, pp.185-194.

[22] Kumar A, Hansson A, Huisken J et al. An FPGA design flow for reconfigurable network-based multi-processor systems on chip. In Proc. the Design, Automation & Test in Europe Conference & Exhibition, April 2007.

[23] Dittmann F, Gotz M, Rettberg A. Model and methodology for the synthesis of heterogeneous and partially reconfigurable systems. In Proc. IEEE International Parallel and Distributed Processing Symposium, March 2007.

[24] Faruque M, Ebi T, Henkel J. Runtime adaptive on-chip communication scheme. In Proc. IEEE/ACM International Conference on Computer-Aided Design, November 2007, pp.26-31.

[25] Zheng L, Cai J, Du M et al. Hybrid communication reconfigurable network on chip for MPSoC. In Proc. the 24th IEEE International Conference on Advanced Information Networking and Applications, April 2010, pp.356-361.

[26] Gohringer D, Becker J. High performance reconfigurable multi-processor-based computing on FPGAs. In Proc. IEEE International Symposium on Parallel & Distributed Processing, Workshops and PhD Forum, April 2010.

[27] Wang C, Zhang J, Zhou X et al. A flexible high speed star network based on peer to peer links on FPGA. In Proc. the 9th IEEE International Symposium on Parallel and Distributed Processing with Applications, May 2011, pp.107-(\d)12.

[28] Wang C, Li X, Zhou X et al. CRAIS: A crossbar based adaptive interconnection scheme. In Proc. the 8th International Symposium on Recon gurable Computing: Architectures, Tools and Applications, March 2012, pp.379-384.

[29] Daya B, Chen C, Subramanian S et al. SCORPIO: A 36core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering. In Proc. the 41st ACM/IEEE International Symposium on Computer Architecture, June 2014, pp.25-36.

[30] Wang C, Li X, Zhang J et al. A star network approach in heterogeneous multiprocessors system on chip. The Journal of Supercomputing, 2012, 62(3):1404-1424.

[31] Freitas H, Carvalho M, Amaral A et al. Reconfigurable crossbar switch architecture for network processors. In Proc. IEEE International Symposium on Circuits and Systems, May 2006.

[32] Young S, Alfke P, Fewer C et al. A high I/O reconfigurable crossbar switch. In Proc. the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, April 2003, pp.3-10.

[33] Rosinger H P. Connecting customized IP to the MicroBlaze soft processor using the Fast Simplex Link (FSL) channel. XILINX®XAPP529, May 2004. http://www.xilinx.com/support/documentation/application notes/xapp529.pdf, Dec. 2014.
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[1] Liu Mingye; Hong Enyu;. Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems[J]. , 1986, 1(2): 83 -92 .
[2] Chen Shihua;. On the Structure of (Weak) Inverses of an (Weakly) Invertible Finite Automaton[J]. , 1986, 1(3): 92 -100 .
[3] Gao Qingshi; Zhang Xiang; Yang Shufan; Chen Shuqing;. Vector Computer 757[J]. , 1986, 1(3): 1 -14 .
[4] Chen Zhaoxiong; Gao Qingshi;. A Substitution Based Model for the Implementation of PROLOG——The Design and Implementation of LPROLOG[J]. , 1986, 1(4): 17 -26 .
[5] Huang Heyan;. A Parallel Implementation Model of HPARLOG[J]. , 1986, 1(4): 27 -38 .
[6] Min Yinghua; Han Zhide;. A Built-in Test Pattern Generator[J]. , 1986, 1(4): 62 -74 .
[7] Tang Tonggao; Zhao Zhaokeng;. Stack Method in Program Semantics[J]. , 1987, 2(1): 51 -63 .
[8] Min Yinghua;. Easy Test Generation PLAs[J]. , 1987, 2(1): 72 -80 .
[9] Zhu Hong;. Some Mathematical Properties of the Functional Programming Language FP[J]. , 1987, 2(3): 202 -216 .
[10] Li Minghui;. CAD System of Microprogrammed Digital Systems[J]. , 1987, 2(3): 226 -235 .

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