›› 2015, Vol. 30 ›› Issue (1): 84-96.doi: 10.1007/s11390-015-1506-5

Special Issue: Computer Architecture and Systems

• Special Section on Computer Architecture and Systems for Big Data • Previous Articles     Next Articles

CRAIS: A Crossbar-Based Interconnection Scheme on FPGA for Big Data

Chao Wang1(王超), Member, CCF, ACM, IEEE, Xi Li1,2(李曦), Senior Member, CCF, Member, ACM, IEEE, Xue-Hai Zhou1(周学海), Senior Member, CCF, Member, ACM, IEEE   

  1. 1 School of Computer Science, University of Science and Technology of China, Hefei 230027, China;
    2 School of Software Engineering, University of Science and Technology of China, Suzhou 215123, China
  • Received:2014-07-15 Revised:2014-12-12 Online:2015-01-05 Published:2015-01-05
  • About author:Chao Wang received his B.S. and Ph.D. degrees from University of Science and Technology of China, Hefei, in 2006 and 2011 respectively, both in computer science. He is an associate processor with School of Computer Science, University of Science and Technology of China, Hefei. His research interests focus on multicore and reconfigurable computing. He has authored more than 60 publications and patents. He is now an editor board member of MICPRO, IET CDT, IJHPSA and IJBPIM. He serves as the publicity chair of HiPEAC 2015 and ISPA 2014, and the guest editor for TCBB and IJPP. He is a member of CCF, ACM, and IEEE.
  • Supported by:

    This work was supported by the National Natural Science Foundation of China under Grant Nos. 61379040, 61272131, 61202053, 61222204, and 61221062, the Natural Science Foundation of Jiangsu Province of China under Grant No. SBK201240198, the Fundamental Research Funds for the Central Universities of China under Grant No. WK0110000034, the Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences (CAS) under Grant No. CARCH201407, and the Strategic Priority Research Program of CAS under Grant No. XDA06010403.

On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip interconnection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the state-of-the-art StarNet approach, while it only utilizes 21%~35% hardware resources of StarNet.

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