›› 2015, Vol. 30 ›› Issue (2): 391-403.doi: 10.1007/s11390-015-1531-4

Special Issue: Computer Architecture and Systems

• Computer Architecture and Systems • Previous Articles     Next Articles

Register Clustering Methodology for Low Power Clock Tree Synthesis

Chao Deng(邓超), Student Member, IEEE, Yi-Ci Cai(蔡懿慈), Senior Member, CCF, ACM, IEEE, Qiang Zhou(周强), Senior Member, CCF, ACM, IEEE   

  1. Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
  • Received:2014-03-26 Revised:2014-11-24 Online:2015-03-05 Published:2015-03-05
  • About author:Chao Deng received his B.S. degree in computer science and technology from Harbin Institute of Technology (HIT), Harbin, in 2010. He is currently pursuing his Ph.D. degree from the EDA Lab, Tsinghua University, Beijing. His research interests include clock network synthesis and optimization.
  • Supported by:

    This work was supported by the National Natural Science Foundation of China under Grant No. 61274031.

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional studies that handle this problem with clock routing or buffer insertion strategy, this paper proposes a novel register clustering methodology in generating the leaf level topology of the clock tree to reduce the power consumption. Three register clustering algorithms called KMR, KSR and GSR are developed and a comprehensive study of them is discussed in this paper. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraint within the clusters at a minimum cost of power consumption. We integrate our algorithms into a classical clock tree synthesis (CTS) flow to test the register clustering methodology on ISPD 2010 benchmark circuits. Experimental results show that all the three register clustering algorithms achieve more than 20% reduction in power consumption without affecting the skew and the maximum latency of the clock tree. As the most effective method among the three algorithms, GSR algorithm achieves a 31% reduction in power consumption as well as a 4% reduction in skew and a 5% reduction in maximum latency. Moreover, the total runtime of the CTS flow with our register clustering algorithms is significantly reduced by almost an order of magnitude.

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