|  Franklin J. The elements of statistical learning:Data mining, inference and prediction. The Mathematical Intelligencer, 2005, 27(2):83-85. Jang J W, Choi S B, Prasanna V K. Energy- and timeefficient matrix multiplication on FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(11):1305-1319. Williams S, Oliker L, Vuduc R et al. Optimization of sparse matrix-vector multiplication on emerging multicore platforms. Parallel Computing, 2009, 35(3):178-194. Catanzaro B, Sundaram N, Keutzer K. Fast support vector machine training and classification on graphics processors. In Proc. the 25th International Conference on Machine Learning, July 2008, pp.104-111. Dean J, Corrado G, Monga R et al. Large scale distributed deep networks. In Advances in Neural Information Processing Systems 25, Pereira F, Burges C, Bottou L, Weinberger K (eds.), Curran Associates, Inc., 2012, pp.1232-1241. Xu C, Dong X, Jouppi N P et al. Design implications of memristor-based RRAM cross-point structures. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2011. Wang Y, Li B, Luo R et al. Energy efficient neural networks for big data analytics. In Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2014. Hu M, Li H, Wu Q et al. Hardware realization of BSB recall function using memristor crossbar arrays. In Proc. the 49th Annual Design Automation Conference, June 2012, pp.498-503. Li B, Shan Y, Hu M et al. Memristor-based approximated computation. In Proc. the International Symposium on Low Power Electronics and Design, September 2013, pp.242- 247. Hu M, Li H, Chen Y et al. Memristor crossbar-based neuromorphic computing system:A case study. IEEE Transactions on Neural Networks and Learning Systems, 2014, 25(10):1864-1878. Li B, Wang Y, Wang Y et al. Training itself:Mixed-signal training acceleration for memristor-based neural network. In Proc. the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014, pp.361-366. Deng Y, Huang P, Chen B et al. RRAM crossbar array with cell selection device:A device and circuit interaction study. IEEE Transactions on Electron Devices, 2013, 60(2):719- 726. Seo K, Kim I, Jung S et al. Analog memory and spiketiming-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device. Nanotechnology, 2011, 22(25):254023. Chang T, Jo S H, Lu W. Short-term memory to long-term memory transition in a nanoscale memristor. ACS Nano, 2011, 5(9):7669-7676. Fang Z, Yu H, Li X et al. Multilayer-based forming-free RRAM devices with excellent uniformity. IEEE Electron Device Letters, 2011, 32(4):566-568. Wong H S P, Lee H Y, Yu S et al. Metal-oxide RRAM. Proceedings of the IEEE, 2012, 100(6):1951-1970. Yu S, Gao B, Fang Z et al. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Advanced Materials, 2013, 25(12):1774-1779. Jiao B, Deng N, Yu J et al. Resisitive switching variability study on 1T1R ALOX/WOx-based RRAM array. In Proc. International Conference of Electron Devices and SolidState Circuits (EDSSC), June 2013. Goux L, Fantini A, Kar G et al. Ultralow sub-500nA operating current high-performance TINAL 2O3 HfO2 HFTiN bipolar RRAM achieved through understandingbased stack-engineering. In Proc. Symposium on VLSI Technology (VLSIT), June 2012, pp.159-160. Young-Fisher K G, Bersuker G, Butcher B et al. Leakage current-forming voltage relation and oxygen gettering in HfOx RRAM devices. IEEE Electron Device Letters, 2013, 34(6):750-752. Yu S, Guan X, Wong H S P. On the stochastic nature of resistive switching in metal oxide RRAM:Physical modeling, monte carlo simulation, and experimental characterization. In Proc. International Electron Devices Meeting (IEDM), December 2011, pp.17.3.1-17.3.4. Degraeve R, Fantini A, Raghavan N et al. Causes and consequences of the stochastic aspect of filamentary RRAM. Microelectronic Engineering, 2015, 147:171-175. Long S, Lian X, Cagli C et al. A model for the set statistics of RRAM inspired in the percolation model of oxide breakdown. IEEE Electron Device Letters, 2013, 34(8):999-1001. Guan X, Yu S, Wong H S. A SPICE compact model of metal oxide resistive switching memory with variations. IEEE Electron Device Letters, 2012, 33(10):1405-1407. Guan X, Yu S, Wong H S P. On the switching parameter variation of metal-oxide RRAM-Part I:Physical modeling and simulation methodology. IEEE Transactions on Electron Devices, 2012, 59(4):1172-1182. Li B, Gu P, Shan Y et al. RRAM-based analog approximate computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(12):1905-1917. Wang Y, Tang T, Xia L et al. Energy efficient RRAM spiking neural network for real time classification. In Proc. the 25th Edition on Great Lakes Symposium on VLSI, May 2015, pp.189-194. Chen A, Lin M R. Variability of resistive switching memories and its impact on crossbar array performance. In Proc. International Reliability Physics Symposium (IRPS), April 2011, pp.MY.7.1-MY.7.4. Lee H, Che P, Wu T et al. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM. In Proc. International Electron Devices Meeting, December 2008. Serrano-Gotarredona T, Masquelier T, Prodromakis T et al. STDP and STDP variations with memristors for spiking neuromorphic learning systems. Frontiers in Neuroscience, 2013, 7(7):2. Tang T, Luo R, Li B et al. Energy efficient spiking neural network design with RRAM devices. In Proc. the 14th International Symposium on Integrated Circuits (ISIC), December 2014, pp.268-271. Querlioz D, Bichler O, Gamrat C. Simulation of a memristor-based spiking neural network immune to device variations. In Proc. International Joint Conference on Neural Networks (IJCNN), July 31-Aug.5, 2011, pp.1775-1781. ITRS teams. International technology roadmap for semiconductors:2013 edition executive summary. http://public.itrs.net/ITRS%201999-2014%20Mtgs,%20Presentations%20&%20Links/2013ITRS/2013Chapters/2013ExecutiveSummary.pdf, Dec. 2015. Dongale T, Patil K, Mullani S et al. Investigation of process parameter variation in the memristor based resistive random access memory (RRAM):Effect of device size variations. Materials Science in Semiconductor Processing, 2015, 35:174-180. Walczyk D, Walczyk C, Schroeder T et al. Resistive switching characteristics of CMOS embedded HfO2-based 1T1R cells. Microelectronic Engineering, 2011, 88(7):1133-1135. Lee S R, Kim Y B, Chang M et al. Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory. In Proc. Symposium on VLSI Technology (VLSIT), June 2012, pp.71-72. Liu B, Li H, Chen Y et al. Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. In Proc. International Conference on ComputerAided Design (ICCAD), November 2014, pp.63-70. Kannan S, Rajendran J, Karri R et al. Sneak-path testing of crossbar-based nonvolatile random access memories. IEEE Transactions on Nanotechnology, 2013, 12(3):413-426. Prakash A, Jana D, Samanta S et al. Self-complianceimproved resistive switching using Ir/TaOx/W cross-point memory. Nanoscale Research Letters, 2013, 8(1):527. Sheu S S, Chiang P C, Lin W P et al. A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme. In Proc. Symposium on VLSI Circuits, June 2009, pp.82-83. Wong S C, Lee G Y, Ma D J. Modeling of interconnect capacitance, delay, and crosstalk in VLSI. IEEE Transactions on Semiconductor Manufacturing, 2000, 13(1):108-111. Govoreanu B, Kar G, Chen Y et al. 10×10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. In Proc. International Electron Devices Meeting (IEDM), December 2011, pp.31.6.1- 31.6.4. Yu S, Gao B, Fang Z et al. A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability:Experimental characterization and large-scale modeling. In Proc. International Electron Devices Meeting (IEDM), December 2012, pp.10.4.1-10.4.4. Kawahara A, Kawai K, Ikeda Y et al. Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM. In Proc. International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), February 2013, pp.220-221. Wang L (ed.). Support Vector Machines:Theory and Applications, Volume 177. Springer-Verlag Berlin Heidelberg, 2005. Bishop C M. Pattern Recognition and Machine Learning. Springer, 2006.