[1] Kim S, Chandra D, Solihin Y. Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proc. the 13th International Conference on Parallel Architectures and Compilation Techniques, September 2004, pp.111-122.[2] Choi I S, Jang S I, Oh C H, Weems C C, Kim S D. A dynamic adaptive converter and management for PRAMbased main memory. Microprocessors and Microsystems, 2013, 37(6/7):554-561.[3] Jang S I, Yoon S K, Park K, Park G H, Kim S D. Data classification management with its interfacing structure for hybrid SLC/MLC PRAM main memory. The Computer Journal, 2014, DOI 10.1093/comjnl/bxu133.[4] Dhiman G, Ayoub R, Rosing T. PDRAM:A hybrid PRAM and DRAM main memory system. In Proc. the 46th ACM/IEEE Design Automation Conference, July 2009, pp.664-669.[5] Yoon S K, Bian M Y, Kim S D. An integrated memory-disk system with buffering adapter and non-volatile memory. Design Automation for Embedded Systems, 2014, 17(3/4):609-626.[6] Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology. ACM SIGARCH Computer Architecture News, 2009, 37(3):24-33.[7] Jung K S, Park J W, Weems C C, Kim S D. A superblock based memory adapter using decoupled dual buffers for hiding the access latency of nonvolatile memory. In Proc. the World Congress on Engineering and Computer Science, October 2011, pp.802-807.[8] Lee B C, Ipek E, Mutlu O, Burger D. Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Computer Architecture News, 2009, 37(3):2- 13.[9] Joo Y, Park S. A hybrid PRAM and STT-RAM cache architecture for extending the lifetime of PRAM caches. IEEE Computer Architecture Letters, 2013, 12(2):55-58.[10] Wang Z, Shan S, Cao T, Gu J, Xu Y, Mu S, Xie Y, Jiménez D A. WADE:Write-back-aware dynamic cache management for NVM-based main memory system. ACM Transactions on Architecture and Code Optimization, 2013, 10(4):Article No. 51.[11] Fedorov V V, Qiu S, Narasimha Reddy A L, Gratz P V. ARI:Adaptive LLC-memory traffic management. ACM Transactions on Architecture and Code Optimization, 2013, 10(4):Article No. 46.[12] Saito S, Oikawa S. Exploration of non-volatile memory management in the OS kernel. In Proc. the 3rd International Conference on Networking and Computing, December 2012, pp.302-306.[13] Kim J K, Lee H G, Choi S, Bahng K I. A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems. In Proc. the 8th ACM International Conference on Embedded Software, October 2008, pp.31-40.[14] Byna S, Chen Y, Sun X H. A taxonomy of data pre-fetching mechanisms. In Proc. International Symposium on Parallel Architectures, Algorithms, and Networks, May 2008, pp.19- 24.[15] Nesbit K, Smith J E. Data cache pre-fetching using a global history buffer. IEEE Micro, 2005, 25(1):90-97.[16] Henning J L. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News, 2006, 34(4):1-17.[17] Henning J L. SPEC CPU2006 memory footprint. ACM SIGARCH Computer Architecture News, 2007, 35(1):84- 89.[18] Woo S C, Ohara M, Torrie E, Singh J P, Gupta A. The SPLASH-2 programs:Characterization and methodological considerations. ACM SIGARCH Computer Architecture News, 1995, 23(2):24-36.[19] Bienia C, Kumar S, Li K. PARSEC vs. SPLASH-2:A quantitative comparison of two multithreaded benchmark suites on chip-multiprocessors. In Proc. IEEE International Symposium on Workload Characterization, September 2008, pp.47-56.[20] Binkert N, Beckmann B, Black G et al. The gem5 simulator. ACM SIGARCH Computer Architecture News, 2011, 39(2):1-7. |