›› 2016, Vol. 31 ›› Issue (4): 836-848.doi: 10.1007/s11390-016-1666-y

Special Issue: Computer Architecture and Systems

• Computer Architecture and Systems • Previous Articles    

Reducing Synchronization Cost for Single-Level Store in Mobile Systems

Yuan-Chao Xu1,2, Member, CCF, ACM, Hu Wan1, Ke-Ni Qiu1, Member, CCF, ACM, Tao Li3, Member, ACM, IEEE, and Wei-Gong Zhang1, Senior Member, CCF   

  1. 1 College of Information Engineering, Capital Normal University, Beijing 100048, China;
    2 State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    3 Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, U.S.A
  • Received:2015-06-01 Revised:2016-04-07 Online:2016-07-05 Published:2016-07-05
  • About author:Yuan-Chao Xu received his B.S. degree in computer science from Beijing Institute of Technology, Beijing, in 1998, M.S. degree in computer science from Beihang University, Beijing, in 2002, and Ph.D. degree in computer architecture from Institute of Computing Technology, Chinese Academy of Sciences, Beijing, in 2012, respectively. He is now an assistant professor in the College of Information Engineering at Capital Normal University, Beijing. His current research interests include operating system support for non-volatile memory technologies and computer architecture for emerging technologies. He is a member of CCF and ACM.
  • Supported by:

    This work was supported by the National Natural Science Foundation of China under Grant Nos. 61502321, 61472260, and 61402302, the Beijing Natural Science Foundation under Grant No. 4143060, the Overseas Visiting Scholar Program of Beijing under Grant No. 067135300100, the State Key Laboratory of Computer Architecture of China under Grant No. CARCH201503, and the Beijing Innovative Teams and Teacher Career Development Program under Grant No. IDHT20150507.

Emerging byte-addressable non-volatile memory technologies, such as phase change memory (PCM) and spintransfer torque RAM (STT-RAM), offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.

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