Reducing the Upper Bound Delay by Optimizing Bank-to-Core Mapping

Nowadays,inter-task interferences are the main difficulty in analyzing the timing behavior of multicores.The timing predictable embedded multicore architecture MERASA,which allows safe worst-case execution time (WCET) estimations,has emerged as an attractive solution.In the architecture,WCET can be estimated by the upper bound delay (UBD) which can be bounded by the interference-aware bus arbiter (IABA) and the dynamic cache partitioning such as columnization or bankization.However,this architecture faces a dilemma between decreasing UBD and efficient shared cache utilization.To obtain tighter WCET estimation,we propose a novel approach that reduces UBD by optimizing bank-to-core mapping on the multicore system with IABA and the two-level partitioned cache.For this,we first present a new UBD computation model based on the analysis of inter-task interference delay,and then put forward the core-sequence optimization method of bank-to-core mapping and the optimizing algorithms with the minimum UBD.Experimental results demonstrate that our approach can reduce WCET from 4% to 37%.