›› 2018, Vol. 33 ›› Issue (1): 145-157.doi: 10.1007/s11390-017-1747-6

Special Issue: Computer Architecture and Systems

• Computer Architecture and Systems • Previous Articles     Next Articles

A Non-Stop Double Buffering Mechanism for Dataflow Architecture

Xu Tan1,2, Student Member, CCF, Xiao-Wei Shen1,2, Xiao-Chun Ye1,3, Member, CCF, Da Wang1, Member, CCF, Dong-Rui Fan1,2,*, Senior Member, CCF, Lunkai Zhang4, Wen-Ming Li1, Member, CCF, Zhi-Min Zhang1, Senior Member, CCF, Zhi-Min Tang1, Distinguished Member, CCF   

  1. 1 State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2 School of Computer and Control Engineering, University of Chinese Academy of Sciences, Beijing 100049, China;
    3 State Key Laboratory of Mathematical Engineering and Advanced Computing, Wuxi 214125, China;
    4 Department of Computer Science, The University of Chicago, Chicago, IL 60637, U.S.A
  • Received:2016-09-02 Revised:2017-03-13 Online:2018-01-05 Published:2018-01-05
  • Contact: Dong-Rui Fan E-mail:fandr@ict.ac.cn
  • About author:Xu Tan received his Bachelor's degree in computer science and technology from Capital Normal University, Beijing, in 2012. He is currently a Ph.D. candidate in Institute of Computing Technology, Chinese Academy of Sciences, Beijing. His main research interests include dataflow architecture and high-performance computer systems.
  • Supported by:

    This work was supported by the National Key Research and Development Program of China under Grant No. 2016YFB0200501, the National Natural Science Foundation of China under Grant Nos. 61332009 and 61521092, the Open Project Program of State Key Laboratory of Mathematical Engineering and Advanced Computing under Grant No. 2016A04, and the Beijing Municipal Science and Technology Commission under Grant No. Z15010101009.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataflow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

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