New non-volatile memory (NVM) technologies are expected to replace main memory DRAM (dynamic random access memory) in the near future. NAND flash technological breakthroughs have enabled wide adoption of solid state drives (SSDs) in storage systems. However, flash-based SSDs, by nature, cannot avoid low endurance problems because each cell only allows a limited number of erasures. This can give rise to critical SSD reliability issues. Since many SSD write operations eventually cause many SSD erase operations, reducing SSD write traffic plays a crucial role in SSD reliability. This paper proposes two NVM-based buffer cache policies which can work together in different layers to maximally reduce SSD write traffic: a main memory buffer cache design named Hierarchical Adaptive Replacement Cache (H-ARC) and an internal SSD write buffer design named Write Traffic Reduction Buffer (WRB). H-ARC considers four factors (dirty, clean, recency, and frequency) to reduce write traffic and improve cache hit ratios in the host. WRB reduces block erasures and write traffic further inside an SSD by effectively exploiting temporal and spatial localities. These two comprehensive schemes significantly reduce total SSD write traffic at each different layer (i.e., host and SSD) by up to 3x. Consequently, they help extend SSD lifespan without system performance degradation.

Key words: buffer cache policy; write buffer; non-volatile memory; solid state drive; flash memory;