Journal of Computer Science and Technology ›› 2020, Vol. 35 ›› Issue (3): 697-720.doi: 10.1007/s11390-020-9414-8

Special Issue: Surveys; Computer Architecture and Systems

• Survey • Previous Articles    

A Survey on Performance Optimization of High-Level Synthesis Tools

Lan Huang1,2, Distinguished Member, CCF, Da-Lin Li1,3, Kang-Ping Wang1,2,*, Teng Gao1, Adriano Tavares4   

  1. 1 College of Computer Science and Technology, Jilin University, Changchun 130012, China;
    2 Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education Jilin University, Changchun 130012, China;
    3 Zhuhai Laboratory of Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education Zhuhai College of Jilin University, Zhuhai 519041, China;
    4 Algorithm Center, University of Minho, Guimaraes 4800058, Portugal
  • Received:2019-01-18 Revised:2019-12-11 Online:2020-05-28 Published:2020-05-28
  • Contact: Kang-Ping Wang E-mail:wangkp@jlu.edu.cn
  • About author:Lan Huang is currently a professor and a supervisor of Ph.D. candidates at Jilin University, Changchun. She received her B.S., M.S. and Ph.D. degrees in computer science and technology from Jilin University, Changchun, in 1994, 1999, and 2003 respectively. She is mainly engaged in intelligent computing, data mining theory and application research, and high-performance computing. She is a distinguished member of CCF.
  • Supported by:
    This work was supported by the National Natural Science Foundation of China under Grant No. 61772227, the Development Project of Jilin Province of China under Grant Nos. 20190201273JC and 2020C003, Guangdong Key Project for Applied Fundamental Research under Grant No. 2018KZDXM076, and Jilin Provincial Key Laboratory of Big Date Intelligent Computing under Grant No. 20180622002JC.

Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

Key words: evaluation criterion; field-programmable gate array (FPGA); high-level synthesis (HLS); performance optimization; quality of results (QoR);

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