Journal of Computer Science and Technology ›› 2021, Vol. 36 ›› Issue (5): 1102-1117.doi: 10.1007/s11390-021-0846-6

Special Issue: Computer Architecture and Systems

• Special Section of 2020 CCF Integrated Circuit Design and Automation Conference • Previous Articles     Next Articles

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption

Yi Zhong1, Jian-Hua Feng1, Senior Member, CCF, Xiao-Xin Cui1,*, Member, CCF, IEEE, and Xiao-Le Cui2, Member, CCF        

  1. 1 Institute of Microelectronics, Peking University, Beijing 100871, China;
    2 Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen 518055, China
  • Received:2020-07-29 Revised:2021-08-25 Online:2021-09-30 Published:2021-09-30
  • About author:Yi Zhong received his B.S. degree in microelectronics from Peking University, Beijing, in 2018. He is currently a Ph.D. candidate in microelectronic and solid-state electronics at the Laboratory of SoC, Institute of Microelectronics, Peking University, Beijing. His current research interests include IC design on neuromorphic system and hardware security.
  • Supported by:
    This work was supported by the 111 Project under Grant No. B18001, the National Key Research and Development Program of China under Grant No. 2018YFB2202605, the Guangdong Science and Technology Project of China under Grant No. 2019B010155002, and the National Natural Science Foundation of China under Grant No. 61672054.

PDF (PC)

17

Supplement

1

Hardware security remains as a major concern in the circuit design flow. Logic block based encryption has been widely adopted as a simple but effective protection method. In this paper, the potential threat arising from the rapidly developing field, i.e., machine learning, is researched. To illustrate the challenge, this work presents a standard attack paradigm, in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic encryption. Backed with validation results obtained from both combinational and sequential benchmarks, the presented attack scheme can specifically accelerate the decryption process of partial keys, which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.

Key words: hardware security; logic encryption; machine learning; neural network; naive Bayes classifier;

[1] Bhunia S, Tehranipoor M. Introduction to hardware security. In Hardware Security:A Hands-on Learning Approach (1st edition), Bhunia S, Tehranipoor M (eds.), Morgan Kaufmann, 2019, pp.1-20. DOI:10.1016/B978-0-12-812477-2.00006-X.
[2] Rajendran J, Sinanoglu O, Karri R. Regaining trust in VLSI design:Design-for-trust techniques. Proceedings of the IEEE, 2014, 102(8):1266-1282. DOI:10.1109/JPROC.2014.2332154.
[3] Hospodar G, Gierlichs B, Mulder E D, Verbauwhede I, Vandewalle J. Machine learning in side-channel analysis:A first study. Journal of Cryptographic Engineering, 2011, 1(4):Article No. 293. DOI:10.1007/s13389-011-0023-x.
[4] Gilmore R, Hanley N, O'Neill M. Neural network based attack on a masked implementation of AES. In Proc. the 2015 IEEE International Symposium on Hardware Oriented Security and Trust, May 2015, pp.106-111. DOI:10.1109/HST.2015.7140247.
[5] Maghrebi H, Portigliatti T, Prouff E. Breaking cryptographic implementations using deep learning techniques. In Proc. the 2016 International Conference on Security, Privacy, and Applied Cryptography Engineering, December 2016, pp.3-26. DOI:10.1007/978-3-319-49445-61.
[6] Das D, Golder A, Danial J, Ghosh S, Raychowdhury A, Sen S. X-DeepSCA:Cross-device deep learning side channel attack. In Proc. the 56th ACM/IEEE Design Automation Conference, June 2019, Article No. 134. DOI:10.1145/3316781.3317934.
[7] Das D, Danial J, Golder A, Ghosh S, Wdhury A R, Sen S. Deep learning side-channel attack resilient AES-256 using current domain signature attenuation in 65nm CMOS. In Proc. the 2020 IEEE Custom Integrated Circuits Conference, March 2020. DOI:10.1109/CICC48029.2020.9075889.
[8] Shan W W, Zhang S, Xu J M, Lu M Y, Shi L X, Yang J. Machine learning assisted side-channel-attack countermeasure and its application on a 28-nm AES circuit. IEEE Journal of Solid-State Circuits, 2020, 55(3):794-804. DOI:10.1109/JSSC.2019.2953855.
[9] Roy J A, Koushanfar F, Markov I L. EPIC:Ending piracy of integrated circuits. In Proc. the 2008 Design, Automation and Test in Europe, March 2008, pp.1069-1074. DOI:10.1109/DATE.2008.4484823.
[10] Rajendran J, Zhang H, Zhang C, Rose G S, Pino Y, Sinanoglu O, Karri R. Fault analysis-based logic encryption. IEEE Transactions on Computers, 2015, 64(2):410-424. DOI:10.1109/TC.2013.193.
[11] Pritika K, Vinodhini M. Logic encryption of combinational circuits. In Proc. the 3rd International Conference on Electronics, Materials Engineering & Nano-Technology, August 2019. DOI:10.1109/IEMENTech48150.2019.8981198.
[12] Kiryakina M A, Kuzmicheva S A, Ivanov M A. Encrypted PRNG by logic encryption. In Proc. the 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering, January 2020, pp.356-358. DOI:10.1109/EIConRus49466.2020.9038921.
[13] Karmakar R, Chatopadhyay S, Kapur R. Encrypt flip-flop:A novel logic encryption technique for sequential circuits. arXiv:1801.04961, 2018. https://arxiv.org/abs/1801.04961, January 2021.
[14] Si?ejkovi? D, Merchant F, Leupers R, Ascheid G, Kegreiss ?. Inter-Lock:Logic encryption for processor cores beyond module boundaries. In Proc. the 2019 IEEE European Test Symposium, May 2019. DOI:10.1109/ETS.2019.8791528.
[15] Karmakar R, Prasad N, Chattopadhyay S, Kapur R, Sengupta I. A new logic encryption strategy ensuring key interdependency. In Proc. the 30th International Conference on VLSI Design and the 16th International Conference on Embedded Systems, January 2017, pp.429-434. DOI:10.1109/VLSID.2017.29.
[16] Juretus K, Savidis I. Reduced overhead gate level logic encryption. In Proc. the 2016 International Great Lakes Symposium on VLSI, May 2016, pp.15-20. DOI:10.1145/2902961.2902972.
[17] Chen X M, Liu Q Y, Wang Y, Xu Q, Yang H Z. Lowoverhead implementation of logic encryption using gate replacement techniques. In Proc. the 18th International Symposium on Quality Electronic Design, March 2017, pp.257-263. DOI:10.1109/ISQED.2017.7918325.
[18] Yasin M, Mazumdar B, Ali S S, Sinanoglu O. Security analysis of logic encryption against the most effective sidechannel attack:DPA. In Proc. the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 2015, pp.97-102. DOI:10.1109/DFT.2015.7315143.
[19] Yasin M, Rajendran J, Sinanoglu O, Karri R. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(9):1411-1424. DOI:10.1109/TCAD.2015.2511144.
[20] Lee Y W, Touba N A. Improving logic obfuscation via logic cone analysis. In Proc. the 16th Latin-American Test Symposium, March 2015. DOI:10.1109/LATW.2015.7102410.
[21] Plaza S M, Markov I L. Solving the third-shift problem in IC piracy with test-aware logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, 34(6):961-971. DOI:10.1109/TCAD.2015.2404876.
[22] Subramanyan P, Ray S, Malik S. Evaluating the security of logic encryption algorithms. In Proc. the 2015 IEEE International Symposium on Hardware Oriented Security and Trust, May 2015, pp.137-143. DOI:10.1109/HST.2015.7140252.
[23] Yasin M, Mazumdar B, Rajendran J, Sinanoglu O. SARLock:SAT attack resistant logic locking. In Proc. the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, May 2016, pp.236-241. DOI:10.1109/HST.2016.7495588.
[24] Xie Y, Srivastava A. Anti-SAT:Mitigating SAT attack on logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38(2):199-207. DOI:10.1109/TCAD.2018.2801220.
[25] Chen Y C. Tree-based logic encryption for resisting SAT attack. In Proc. the 26th IEEE Asian Test Symposium, November 2017, pp.46-51. DOI:10.1109/ATS.2017.21.
[26] Shen Y Q, Rezaei A, Zhou H. SAT-based bit-flipping attack on logic encryptions. In Proc. the 2018 Design, Automation & Test in Europe Conference & Exhibition, March 2018, pp.629-632. DOI:10.23919/DATE.2018.8342086.
[27] Shen Y Q, Li Y, Kong S Y, Rezaei A, Zhou H. SigAttack:New high-level SAT-based attack on logic encryptions. In Proc. the 2019 Design, Automation & Test in Europe Conference & Exhibition, March 2019, pp.940-943. DOI:10.23919/DATE.2019.8714924.
[28] Kasarabada Y, Chen S Y, Vemuri R. On SATbased attacks on encrypted sequential logic circuits. In Proc. the 20th International Symposium on Quality Electronic Design, March 2019, pp.204-211. DOI:10.1109/ISQED.2019.8697421.
[29] Rajendran J, Pino Y, Sinanoglu O, Karri R. Logic encryption:A fault analysis perspective. In Proc. the 2012 Design, Automation & Test in Europe Conference & Exhibition, March 2012, pp.953-958. DOI:10.1109/DATE.2012.6176634.
[30] Karmakar R, Chattopadhyay S, Kapur R. Enhancing security of logic encryption using embedded key generation unit. In Proc. the 2017 International Test Conference in Asia (ITC-Asia), September 2017, pp.131-136. DOI:10.1109/ITC-ASIA.2017.8097127.
[31] Mobaraki S, Amirkhani A, Atani R E. A novel PUF based logic encryption technique to prevent SAT attacks and trojan insertion. In Proc. the 9th International Symposium on Telecommunications, December 2018, pp.507-513. DOI:10.1109/ISTEL.2018.8661086.
[1] Jia-Jun Li, Ke Wang, Hao Zheng, and Ahmed Louri. GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators [J]. Journal of Computer Science and Technology, 2023, 38(1): 115-127.
[2] Xiao-Bing Chen, Hao Qi, Shao-Hui Peng, Yi-Min Zhuang, Tian Zhi, and Yun-Ji Chen. Tetris: A Heuristic Static Memory Management Framework for Uniform Memory Multicore Neural Network Accelerators [J]. Journal of Computer Science and Technology, 2022, 37(6): 1255-1270.
[3] Xu-Gang Wu, Hui-Jun Wu, Xu Zhou, Xiang Zhao, and Kai Lu. Towards Defense Against Adversarial Attacks on Graph Neural Networks via Calibrated Co-Training [J]. Journal of Computer Science and Technology, 2022, 37(5): 1161-1175.
[4] Xiao-Qing Deng, Bo-Lin Chen, Wei-Qi Luo, and Da Luo. Universal Image Steganalysis Based on Convolutional Neural Network with Global Covariance Pooling [J]. Journal of Computer Science and Technology, 2022, 37(5): 1134-1145.
[5] Zhi-Jing Wu, Yi-Qun Liu, Jia-Xin Mao, Min Zhang, and Shao-Ping Ma. Leveraging Document-Level and Query-Level Passage Cumulative Gain for Document Ranking [J]. Journal of Computer Science and Technology, 2022, 37(4): 814-838.
[6] Linfeng Shen, Yuchi Chen, and Jiangchuan Liu. Gaze-Assisted Viewport Control for 360° Video on Smartphone [J]. Journal of Computer Science and Technology, 2022, 37(4): 906-918.
[7] Zheng Chen, Xiao-Nan Fang, and Song-Hai Zhang. Local Homography Estimation on User-Specified Textureless Regions [J]. Journal of Computer Science and Technology, 2022, 37(3): 615-625.
[8] Hua-Peng Wei, Ying-Ying Deng, Fan Tang, Xing-Jia Pan, and Wei-Ming Dong. A Comparative Study of CNN- and Transformer-Based Visual Style Transfer [J]. Journal of Computer Science and Technology, 2022, 37(3): 601-614.
[9] Xiao-Zheng Xie, Jian-Wei Niu, Xue-Feng Liu, Qing-Feng Li, Yong Wang, Jie Han, and Shaojie Tang. DG-CNN: Introducing Margin Information into Convolutional Neural Networks for Breast Cancer Diagnosis in Ultrasound Images [J]. Journal of Computer Science and Technology, 2022, 37(2): 277-294.
[10] Xin-Feng Wang, Xiang Zhou, Jia-Hua Rao, Zhu-Jin Zhang, and Yue-Dong Yang. Imputing DNA Methylation by Transferred Learning Based Neural Network [J]. Journal of Computer Science and Technology, 2022, 37(2): 320-329.
[11] Xin Zhang, Siyuan Lu, Shui-Hua Wang, Xiang Yu, Su-Jing Wang, Lun Yao, Yi Pan, and Yu-Dong Zhang. Diagnosis of COVID-19 Pneumonia via a Novel Deep Learning Architecture [J]. Journal of Computer Science and Technology, 2022, 37(2): 330-343.
[12] Geun Yong Kim, Joon-Young Paik, Yeongcheol Kim, and Eun-Sun Cho. Byte Frequency Based Indicators for Crypto-Ransomware Detection from Empirical Analysis [J]. Journal of Computer Science and Technology, 2022, 37(2): 423-442.
[13] Jian-Zhe Zhao, Xing-Wei Wang, Ke-Ming Mao, Chen-Xi Huang, Yu-Kai Su, and Yu-Chen Li. Correlated Differential Privacy of Multiparty Data Release in Machine Learning [J]. Journal of Computer Science and Technology, 2022, 37(1): 231-251.
[14] Dan-Hao Zhu, Xin-Yu Dai, Jia-Jun Chen. Pre-Train and Learn: Preserving Global Information for Graph Neural Networks [J]. Journal of Computer Science and Technology, 2021, 36(6): 1420-1430.
[15] Feng Wang, Guo-Jie Luo, Guang-Yu Sun, Yu-Hao Wang, Di-Min Niu, Hong-Zhong Zheng. Area Efficient Pattern Representation of Binary Neural Networks on RRAM [J]. Journal of Computer Science and Technology, 2021, 36(5): 1155-1166.
Viewed
Full text


Abstract

Cited
  Shared   
  Discussed   
[1] Zhou Di;. A Recovery Technique for Distributed Communicating Process Systems[J]. , 1986, 1(2): 34 -43 .
[2] Li Wei;. A Structural Operational Semantics for an Edison Like Language(2)[J]. , 1986, 1(2): 42 -53 .
[3] Chen Shihua;. On the Structure of Finite Automata of Which M Is an(Weak)Inverse with Delay τ[J]. , 1986, 1(2): 54 -59 .
[4] Li Wanxue;. Almost Optimal Dynamic 2-3 Trees[J]. , 1986, 1(2): 60 -71 .
[5] Feng Yulin;. Recursive Implementation of VLSI Circuits[J]. , 1986, 1(2): 72 -82 .
[6] Liu Mingye; Hong Enyu;. Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems[J]. , 1986, 1(2): 83 -92 .
[7] Wang Xuan; Lü Zhimin; Tang Yuhai; Xiang Yang;. A High Resolution Chinese Character Generator[J]. , 1986, 1(2): 1 -14 .
[8] C.Y.Chung; H.R.Hwa;. A Chinese Information Processing System[J]. , 1986, 1(2): 15 -24 .
[9] Sun Zhongxiu; Shang Lujun;. DMODULA:A Distributed Programming Language[J]. , 1986, 1(2): 25 -31 .
[10] Gao Qingshi; Zhang Xiang; Yang Shufan; Chen Shuqing;. Vector Computer 757[J]. , 1986, 1(3): 1 -14 .

ISSN 1000-9000(Print)

         1860-4749(Online)
CN 11-2296/TP

 Home
Editorial Board
Author Guidelines
Subscription		 Journal of Computer Science and Technology
Institute of Computing Technology, Chinese Academy of Sciences
P.O. Box 2704, Beijing 100190 P.R. China
Tel.:86-10-62610746
E-mail: jcst@ict.ac.cn
 
  Copyright ©2015 JCST, All Rights Reserved