Journal of Computer Science and Technology ›› 2021, Vol. 36 ›› Issue (5): 1118-1132.doi: 10.1007/s11390-021-0904-0

Special Issue: Computer Architecture and Systems

• Special Section of 2020 CCF Integrated Circuit Design and Automation Conference • Previous Articles     Next Articles

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

Xiao-Jing Zha, Yin-Shui Xia*, Shang-Luan Xie, and Zhu-Fei Chu*, Member, CCF, IEEE        

  1. Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
  • Received:2020-08-19 Revised:2021-08-05 Online:2021-09-30 Published:2021-09-30
  • About author:Xiao-Jing Zha received her B.S. degree in communication engineering from Anhui Normal University, Wuhu, in 2016. She is currently working toward her Ph.D. degree in communication and information system at Ningbo University, Ningbo. Her research interests include electronic design automation and logic mapping.
  • Supported by:
    This work was partially supported by the National Natural Science Foundation of China under Grant Nos. U1709218 and 61871242.

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL) circuit, defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits. However, less effort has been made to improve circuit delay by defect-tolerant strategies. In this paper, the factors affecting the delay of mapped circuits are analyzed, and the path-tree based defect-tolerant mapping method for the delay optimization is proposed. From the logic-domain, the terminology of the path tree is presented, and the logic circuit is first partitioned into multiple path trees. Then, the mapping areas in the physic-domain are pre-planned for (near) critical path trees. During the mapping process, the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting; (near) critical path trees are mapped with priority, while the others are mapped in a hierarchical way. Finally, an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method. Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.

Key words: nanohybrid circuit; defect-tolerant mapping; delay optimization;

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