Journal of Computer Science and Technology


Automatic Target Description File Generation

Hong-Na Geng1,2(耿洪娜), Student Member, CCF, Fang Lv1,*(吕方), Member, CCF, Ming Zhong1,2(钟茗), Student Member, CCF, Hui-Min Cui1,2(崔慧敏), Member, CCF, Jingling Xue3, Senior Member, IEEE, and Xiao-Bing Feng1,2(冯晓兵), Senior Member, CCF   

  1. 1State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
    2University of Chinese Academy of Sciences, Beijing 100049, China
    3School of Computer Science and Engineering, University of New South Wales, Sydney, NSW 2052, Australia

Agile hardware design is gaining increasing momentum and bringing new chips in larger quantities to market faster. However, it also takes new challenges for compiler developers to retarget existing compilers to these new chips in shorter time than ever before. Currently, retargeting a compiler backend, e.g., an LLVM backend to a new target requires compiler developers to write manually a set of target description files (totalling 10,300+ LOC for RISC-V in LLVM), which is error-prone and time consuming. In this paper, we introduce a new approach, Automatic Target description file Generation (ATG), which accelerates the generation of a compiler backend for a new target by generating its target description files automatically. Given a new target, ATG proceeds in two stages. First, ATG synthesizes a small list of target-specific properties and a list of code-layout templates from the target description files of a set of existing targets with similar instruction set architectures (ISAs). Second, ATG requests compiler developers to fill in the information for each instruction in the new target in tabular form according to the list of target-specific properties synthesized and then generates its target description files automatically according to the list of code-layout templates synthesized. The first stage can often be reused by different new targets sharing similar ISAs. We evaluated ATG using nine RISC-V instruction sets drawn from a total of 1,029 instructions in LLVM 12.0. ATG enables compiler developers to generate compiler backends for these ISAs that emit the same assembly code as the existing compiler backends for RISC-V but with significantly less development effort (by specifying each instruction in terms of up to 61 target-specific properties only).


随着敏捷硬件设计技术的快速发展,更多的新型芯片被更快速地推向市场,这给编译器开发人员带来了新的挑战,他们要花比以往更短的时间,在现有编译器中支持这些新型芯片。目前,编译器开发人员需要手动编写一组目标描述文件,来为新目标平台做编译器后端的支持(例如,在LLVM后端中支持RISC-V平台,需要编写10300多行的的目标描述文件代码),这既耗费大量时间又容易出错。在本文中,我们提出了一种自动目标描述文件生成( ATG )的方法,它通过自动生成目标描述文件,加速为新目标平台生成编译器后端的过程。对于给定的新目标平台,ATG 分两个阶段进行目标描述文件生成。首先,ATG 从一组具有相似指令集架构(ISA)的现有平台的目标描述文件中,合成一小部分目标平台特性相关的属性列表,以及一系列代码布局模板。其次,ATG 需要芯片开发人员根据第一步中合成的目标平台特性相关属性列表,以表格的形式填写新目标平台中的每条指令的信息,最后根据合成的代码布局模板列表自动生成其目标描述文件。ATG的第一个阶段通常可以被ISA相似的不同目标平台重复使用。我们使用了9个RISC-V 指令集(共计1,029条指令),在LLVM 12.0中对ATG进行了测试。测试结果表明,借助ATG,芯片开发人员只需要为每条指令填写不超过61个特定的属性值,便可实现为这些目标平台生成编译器后端。ATG生成的后端可以与RISC-V的现有编译器后端产生相同的汇编代码,但开发工作量明显减少。
1、 研究背景(context):
2、 目的(Objective):
目前,编译器开发人员需要手动编写一组目标描述文件,来为新目标平台做编译器后端的支持(例如,在LLVM后端中支持RISC-V平台,需要编写10300多行的的目标描述文件代码),这既耗费大量时间又容易出错。在本文中,我们提出了一种自动目标描述文件生成( ATG )的方法,它通过自动生成目标描述文件,加速为新目标平台生成编译器后端的过程。
3、 方法(Method):
对于给定的新目标平台,ATG 分两个阶段进行目标描述文件生成。首先,ATG 从一组具有相似指令集架构(ISA)的现有平台的目标描述文件中,合成一小部分目标平台特性相关的属性列表,以及一系列代码布局模板。其次,ATG 需要芯片开发人员根据第一步中合成的目标平台特性相关属性列表,以表格的形式填写新目标平台中的每条指令的信息,最后根据合成的代码布局模板列表自动生成其目标描述文件。ATG的第一个阶段通常可以被ISA相似的不同目标平台重复使用。
4、 结果(Result & Findings):
我们使用了9个RISC-V 指令集(共计1,029条指令,在LLVM 12.0中对ATG进行了测试。测试结果表明,借助ATG,芯片开发人员只需要为每条指令填写不超过61个特定的属性值,便可实现为这些目标平台生成编译器后端。ATG生成的后端可以与RISC-V的现有编译器后端产生相同的汇编代码(ATG生成的后端可以为16个C/C++ SPEC2017基准测试程序和大约15,600个LLVM 回归测试生成准确的代码),但开发工作量明显减少。
5、 结论(Conclusions):
我们提出了ATG,它可以利用一个简单的目标平台特性相关的属性列表,生成目标描述文件,用于在编译器中为新目标平台做支持。ATG大大加速了对超过9个RISC-V ISA的编译器后端生成过程,同时ATG生成的后端可以为16个C/C++ SPEC2017基准测试程序和大约15,600个LLVM 回归测试生成准确的代码。ATG 以黑盒的方式工作,除了少量必不可少的属性外,整个过程不需要人工干预。我们仍在探索编译器内部的可重用模块和规律。ATG关注定制化芯片中可重定向性的根本变化,同时致力于逐步减少开发人员的人工参与。

Key words: retargetability, compiler, target description, target backend, automatic generator


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