Journal of Computer Science and Technology ›› 2023, Vol. 38 ›› Issue (2): 273-288.doi: 10.1007/s11390-023-2554-x

Special Issue: Surveys; Computer Architecture and Systems

• Special Section on Approximate Computing Circuits and Systems • Previous Articles     Next Articles

A Survey of Reliability Issues Related to Approximate Circuits

Zhen Wang1 (王　真), Member, CCF, Rong-Chen Xu1 (徐荣臣), Jia-Cheng Chen1 (陈嘉诚), and Jie Xiao2, * (肖　杰)   

  1. 1 College of Computer Science and Technology, Shanghai University of Electric Power, Shanghai 200090, China

    2 College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou 310000, China

  • Received:2022-06-01 Revised:2022-12-19 Accepted:2023-02-08 Online:2023-05-10 Published:2023-05-10
  • Contact: Jie Xiao E-mail:xiaojiexqj@zjut.edu.cn
  • About author:Jie Xiao received his Ph.D. degree in computer system architecture from Tongji University, Shanghai, in 2013. He is currently working with the College of Computer Science and Technology, Zhejiang University of Technology, Hangzhou. His current research interests include reliability evaluation and fault-tolerant design, deep learning and combinatorial optimization-computation. He has coauthored one book and published more than 30 technical papers in refereed international journals including IEEE TC, TR and TCAD.
  • Supported by:
    This work was partially supported by the Natural Science Foundation of Shanghai under Grant No. 20ZR1455900, and the State Key Laboratory of Computer Architecture (Institute of Computing Technology, Chinese Academy of Sciences) under Grant No. CARCHA202005.

PDF

35

Supplement

1

As one of the most promising paradigms of integrated circuit design, the approximate circuit has aroused widespread concern in the scientific community. It takes advantage of the inherent error tolerance of some applications and relaxes the accuracy for reductions in area and power consumption. This paper aims to provide a comprehensive survey of reliability issues related to approximate circuits, which covers three concerns: error characteristic analysis, reliability and test, and reliable design involving approximate circuits. The error characteristic analysis is used to compare the outputs of the approximate circuit with those of its precise counterpart, which can help to find the most appropriate approximate design for a specific application in the large design space. With the approximate design getting close to physical realization, manufacturing defects and operational faults are inevitable; therefore, the reliability prediction and vulnerability test become increasingly important. However, the research on approximate circuit reliability and test is insufficient and needs more attention. Furtherly, although there is some existing work combining the approximate design with fault tolerant techniques, the reliability-enhancement approaches for approximate circuits are lacking.

Key words: approximate circuit; error metrics; fault tolerance; test; reliability ;

[1] Moore G E. Cramming more components onto integrated circuits. IEEE Solid-State Circuits Society Newsletter, 2006, 11(3): 33–35. DOI: 10.1109/N-SSC.2006.4785860.
[2] Dennard R H, Spampinato D P. Differential charge transfer sense amplifier. United States Patent 3949381. 1976-04-06.
[3] Liu G, Zhang Z R. Statistically certified approximate logic synthesis. In Proc. the 2017 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2017, pp.344–351. DOI: 10.1109/ICCAD.2017.8203798.
[4] Chen C Y, Choi J, Gopalakrishnan K, Srinivasan V, Venkataramani S. Exploiting approximate computing for deep learning acceleration. In Proc. the 2018 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2018, pp.821–826. DOI: 10.23919/DATE.2018.8342119.
[5] Han J, Orshansky M. Approximate computing: An emerging paradigm for energy-efficient design. In Proc. the 2013 IEEE European Test Symposium, May 2013. DOI: 10.1109/ETS.2013.6569370.
[6] Yazdanbakhsh A, Park J, Sharma H, Lotfi-Kamran P, Esmaeilzadeh H. Neural acceleration for GPU throughput processors. In Proc. the 48th International Symposium on Microarchitecture, Dec. 2015, pp.482–493. DOI: 10.1145/2830772.2830810.
[7] Samadi M, Jamshidi D A, Lee J, Mahlke S. Paraprox: Pattern-based appoximation for data parallel applications. In Proc. the 19th International Conference on Architectural Support for Programming Languages and Operating Systems, Feb. 2014, pp.35–50. DOI: 10.1145/2541940.2541948.
[8] Sidiroglou-Douskos S, Misailovic S, Hoffmann H, Rinard M. Managing performance vs accuracy trade-offs with loop perforation. In Proc. the 19th ACM SIGSOFT Symposium and the 13th European Conference on Foundations of Software Engineering, Sept. 2011, pp.124–134. DOI: 10.1145/2025113.2025133.
[9] Yang Z X, Jain A, Liang J H, Han J, Lombardi F. Approximate XOR/XNOR-based adders for inexact computing. In Proc. the 13th IEEE International Conference on Nanotechnology, Aug. 2013, pp.690–693. DOI: 10.1109/NANO.2013.6720793.
[10] Ramasamy M, Narmadha G, Deivasigamani S. Carry based approximate full adder for low power approximate computing. In Proc. the 7th International Conference on Smart Computing & Communications, Jun. 2019. DOI: 10.1109/ICSCC.2019.8843644.
[11] Liu W Q, Qian L Y, Wang C H, Jiang H L, Han J, Lombardi F. Design of approximate radix-4 booth multipliers for error-tolerant computing. IEEE Trans. Computers, 2017, 66(8): 1435–1441. DOI: 10.1109/TC.2017.2672976.
[12] Cao T, Liu W Q, Zhu Y Y. Design of approximate Booth multipliers for error-tolerant computing. Microelectronics Computer, 2018, 35(7): 67-71. DOI: 10.19304/j.cnki.issn1000-7180.2018.07.014. (in Chinese)
[13] Liu Z H, Yazdanbakhsh A, Park T, Esmaeilzadeh H, Kim N S. SiMul: An algorithm-driven approximate multiplier design for machine learning. IEEE Micro, 2018, 38(4): 50–59. DOI: 10.1109/MM.2018.043191125.
[14] Ansari M S, Cockburn B F, Han J. An improved logarithmic multiplier for energy-efficient neural computing. IEEE Trans. Computers, 2021, 70(4): 614–625. DOI: 10.1109/TC.2020.2992113.
[15] Gielen G, De Wit P, Maricau E, Loeckx J, Martín-Martínez J, Kaczer B, Groeseneken G, Rodríguez R, Nafría M. Emerging yield and reliability challenges in nanometer CMOS technologies. In Proc. the 2008 Conference on Design, Automation and Test in Europe, Mar. 2008, pp.1322–1327. DOI: 10.1145/1403375.1403694.
[16] Mohanram K, Touba N A. Partial error masking to reduce soft error failure rate in logic circuits. In Proc. the 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2003, pp.433–440. DOI: 10.1109/DFTVS.2003.1250141.
[17] Choudhury M R, Mohanram K. Low cost concurrent error masking using approximate logic circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(8): 1163–1176. DOI: 10.1109/TCAD.2013.2250581.
[18] Choudhury M R, Mohanram K. Approximate logic circuits for low overhead, non-intrusive concurrent error detection. In Proc. the 2008 Conference on Design, Automation and Test in Europe, Mar. 2008, pp.903–908. DOI: 10.1145/1403375.1403593.
[19] Martin H, Entrena L, Dupuis S, Natale G D. A novel use of approximate circuits to thwart hardware Trojan insertion and provide obfuscation. In Proc. the 24th International Symposium on On-Line Testing and Robust System Design, Jul. 2018, pp.41–42. DOI: 10.1109/IOLTS.2018.8474077.
[20] Liang J H, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans. Computers, 2013, 62(9): 1760–1771. DOI: 10.1109/TC.2012.146.
[21] Gebregiorgis A, Kiamehr S, Tahoori M B. Error propagation aware timing relaxation for approximate near threshold computing. In Proc. the 54th Annual Design Automation Conference, Jun. 2017, Article No. 77. DOI: 10.1145/3061639.3062240
[22] Yu C C, Hayes J P. Scalable and accurate estimation of probabilistic behavior in sequential circuits. In Proc. the 28th VLSI Test Symposium, Apr. 2010, pp.165–170. DOI: 10.1109/VTS.2010.5469586.
[23] Kulkarni P, Gupta P, Ercegovac M. Trading accuracy for power with an underdesigned multiplier architecture. In Proc. the 24th Internatioal Conference on VLSI Design, Jan. 2011, pp.346–351. DOI: 10.1109/VLSID.2011.51.
[24] Liu C, Han J, Lombardi F. An analytical framework for evaluating the error characteristics of approximate adders. IEEE Trans. Computers, 2015, 64(5): 1268–1281. DOI: 10.1109/TC.2014.2317180.
[25] Jiang H L, Han J, Qiao F, Lombardi F. Approximate radix-8 booth multipliers for low-power and high-performance operation. IEEE Trans. Computers, 2016, 65(8): 2638–2644. DOI: 10.1109/TC.2015.2493547.
[26] Roy A S, Biswas R, Dhar A S. On fast and exact computation of error metrics in approximate LSB adders. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2020, 28(4): 876–889. DOI: 10.1109/TVLSI.2020.2967149.
[27] Mrazek V, Hrbacek R, Vasicek Z, Sekanina L. EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. In Proc. the 2017 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2017, pp.258–261. DOI: 10.23919/DATE.2017.7926993.
[28] Biersack J P, Haggmark L G. A Monte Carlo computer program for the transport of energetic ions in amorphous targets. Nuclear Instruments and Methods, 1980, 174(1/2): 257–269. DOI: 10.1016/0029-554X(80)90440-1.
[29] Mazahir S, Hasan O, Hafiz R, Shafique M, Henkel J. Probabilistic error modeling for approximate adders. IEEE Trans. Computers, 2017, 66(3): 515–530. DOI: 10.1109/TC.2016.2605382.
[30] Venkatesan R, Agarwal A, Roy K, Raghunathan A. MACACO: Modeling and analysis of circuits for approximate computing. In Proc. the 2011 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2011, pp.667–673. DOI: 10.1109/ICCAD.2011.6105401.
[31] Bonnot J, Menard D, Desnos K. Fast kriging-based error evaluation for approximate computing systems. In Proc. the 2020 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2020, pp.1384–1389. DOI: 10.23919/DATE48585.2020.9116320.
[32] Ayub M K, Hasan O, Shafique M. Statistical error analysis for low power approximate adders. In Proc. the 54th Annual Design Automation Conference, Jun. 2017, Article No. 75. DOI: 10.1145/3061639.3062319.
[33] Gupta V, Mohapatra D, Park S P, Raghunathan A, Roy K. IMPACT: Imprecise adders for low-power approximate computing. In Proc. the 2011 IEEE/ACM International Symposium on Low Power Electronics and Design, Aug. 2011, pp.409–414. DOI: 10.1109/ISLPED.2011.5993675.
[34] Gupta V, Mohapatra D, Raghunathan A, Roy K. Low-power digital signal processing using approximate adders. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(1): 124–137. DOI: 10.1109/TCAD.2012.2217962.
[35] Shafique M, Ahmad W, Hafiz R, Henkel J. A low latency generic accuracy configurable adder. In Proc. the 52nd Annual Design Automation Conference, Jun. 2015, Article No. 86. DOI: 10.1145/2744769.2744778.
[36] Almurib H A F, Kumar T N, Lombardi F. Inexact designs for approximate low power addition by cell replacement. In Proc. the 2016 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2016, pp.660–665. DOI: 10.3850/9783981537079_0042.
[37] Rezaalipour M, Rezaalipour M, Dehyadegari M, Bojnordi M N. AxMAP: Making approximate adders aware of input patterns. IEEE Trans. Computers, 2020, 69(6): 868–882. DOI: 10.1109/TC.2020.2968905.
[38] Kahng A B, Kang S. Accuracy-configurable adder for approximate arithmetic designs. In Proc. the 49th Annual Design Automation Conference, Jun. 2012, pp.820–825. DOI: 10.1145/2228360.2228509.
[39] Kulkarni P, Gupta P, Ercegovac M D. Trading accuracy for power in a multiplier architecture. Journal of Low Power Electronics, 2011, 7(4): 490–501. DOI: 10.1166/jolpe.2011.1157.
[40] Lin C H, Lin I C. High accuracy approximate multiplier with error correction. In Proc. the 31st IEEE International Conference on Computer Design, Oct. 2013, pp.33–38. DOI: 10.1109/ICCD.2013.6657022.
[41] Maheshwari N, Yang Z X, Han J, Lombardi F. A design approach for compressor based approximate multipliers. In Proc. the 28th International Conference on VLSI Design, Jan. 2015, pp.209–214. DOI: 10.1109/VLSID.2015.41.
[42] Momeni A, Han J, Montuschi P, Lombardi F. Design and analysis of approximate compressors for multiplication. IEEE Trans. Computers, 2015, 64(4): 984–994. DOI: 10.1109/TC.2014.2308214.
[43] Mazahir S, Hasan O, Hafiz R, Shafique M. Probabilistic error analysis of approximate recursive multipliers. IEEE Trans. Computers, 2017, 66(11): 1982–1990. DOI: 10.1109/TC.2017.2709542.
[44] Sengupta D, Sapatnekar S S. FEMTO: Fast error analysis in multipliers through topological traversal. In Proc. the 2015 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2015, pp.294–299. DOI: 10.1109/ICCAD.2015.7372583.
[45] Sunny A, Mathew B K, Dhanusha P B. Area efficient high speed approximate multiplier with carry predictor. Procedia Technology, 2016, 24: 1170–1177. DOI: 10.1016/j.protcy.2016.05.072.
[46] Kim M S, Del Barrio A A, Oliveira L T, Hermida R, Bagherzadeh N. Efficient Mitchell’s approximate log multipliers for convolutional neural networks. IEEE Trans. Computers, 2019, 68(5): 660–675. DOI: 10.1109/TC.2018.2880742.
[47] Vasicek Z. Formal methods for exact analysis of approximate circuits. IEEE Access, 2019, 7: 177309–177331. DOI: 10.1109/ACCESS.2019.2958605.
[48] Froehlich S, GroBe D, Drechsler R. One method—All error-metrics: A three-stage approach for error-metric evaluation in approximate computing. In Proc. Design, Autom. Test Eur ConfExhib. (DATE), Mar. 2019, pp.284–287. DOI: 10.23919/DATE.2019.8715138.
[49] Soeken M, Große D, Chandrasekharan A, Drechsler R. BDD minimization for approximate computing. In Proc. the 21st Asia and South Pacific Design Automation Conference, Jan. 2016, pp.474–479. DOI: 10.1109/ASPDAC.2016.7428057.
[50] Wendler A, Keszocze O. A fast BDD minimization framework for approximate computing. In Proc. the 2020 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2020, pp.1372–1377. DOI: 10.23919/DATE48585.2020.9116296.
[51] Froehlich S, Große D, Drechsler R. One method-all error-metrics: A three-stage approach for error-metric evaluation in approximate computing. In Proc. the 2019 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2019, pp.284–287. DOI: 10.23919/DATE.2019.8715138.
[52] Chandrasekharan A, Soeken M, Große D, Drechsler R. Precise error determination of approximated components in sequential circuits with model checking. In Proc. the 53rd Annual Design Automation Conference, Jun. 2016, Article No. 129. DOI: 10.1145/2897937.2898069.
[53] Češka M, Matyaš J, Mrazek V, Sekanina L, Vasicek Z, Vojnar T. Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished. In Proc. the 2017 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2017, pp.416-423. DOI: 10.1109/ICCAD.2017.8203807.
[54] Anghel L, Benabdenbi M, Bosio A, Vatajelu E I. Test and reliability in approximate computing. In Proc. the 2017 International Mixed Signals Testing Workshop, Jul. 2017. DOI: 10.1109/IMS3TW.2017.7995210.
[55] Jiang J H, Lu G M, Wang Z. Methods for approximate adders reliability estimation based on PTM model. In Proc. the 23rd Pacific Rim International Symposium on Dependable Computing, Dec. 2018, pp.221–222. DOI: 10.1109/PRDC.2018.00038.
[56] Wang Z, Zhang G F, Ye J, Jiang J H, Li F Y, Wang Y. Accurate reliability analysis methods for approximate computing circuits. Tsinghua Science and Technology, 2022, 27(4): 729–740. DOI: 10.26599/TST.2020.9010032.
[57] Jiang J H, Wang T, Wang Z. Probability gate model based methods for approximate arithmetic circuits reliability estimation. CCF Trans. High Performance Computing, 2021, 3(2): 201–219. DOI: 10.1007/s42514-020-00058-1.
[58] Wang Z, Jiang J H, Wang T. Failure probability analysis and critical node determination for approximate circuits. Integration, 2019, 68: 122–128. DOI: 10.1016/j.vlsi.2019.05.008.
[59] Bosio A, Di Carlo S, Girard P, Sanchez E, Savino A, Sekanina L, Traiola M, Vasicek Z, Virazel A. Design, verification, test and in-field implications of approximate computing systems. In Proc. the 2020 IEEE European Test Symposium, May 2020. DOI: 10.1109/ETS48528.2020.9131557.
[60] Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. On the comparison of different ATPG approaches for approximate integrated circuits. In Proc. the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits Systems, Apr. 2018, pp.85–90. DOI: 10.1109/DDECS.2018.00022.
[61] Chandrasekharan A, Eggersglüß S, Große D, Drechsler R. Approximation-aware testing for approximate circuits. In Proc. the 23rd Asia and South Pacific Design Automation Conference, Jan. 2018, pp.239–244. DOI: 10.1109/ASPDAC.2018.8297312.
[62] Traiola M, Virazel A, Girard P, Barbarcschi M, Bosio A. Investigation of mean-error metrics for testing approximate integrated circuits. In Proc. the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct. 2018. DOI: 10.1109/DFT.2018.8602939.
[63] Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Testing approximate digital circuits: Challenges and opportunities. In Proc. the 19th IEEE Latin-American Test Symposium, Mar. 2018. DOI: 10.1109/LATW.2018.8349681.
[64] Wali I, Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Towards approximation during test of integrated circuits. In Proc. the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, Apr. 2017, pp.28–33. DOI: 10.1109/DDECS.2017.7934574.
[65] Anghel L, Benabdenbi M, Bosio A, Traiola M, Vatajelu E I. Test and reliability in approximate computing. Journal of Electronic Testing, 2018, 34(4): 375–387. DOI: 10.1007/s10836-018-5734-9.
[66] Gebregiorgis A, Tahoori M B. Test pattern generation for approximate circuits based on Boolean satisfiability. In Proc. the 2019 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2019, pp.1028–1033. DOI: 10.23919/DATE.2019.8714898.
[67] Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. A test pattern generation technique for approximate circuits based on an ILP-formulated pattern selection procedure. IEEE Trans. Nanotechnology, 2019, 18: 849–857. DOI: 10.1109/TNANO.2019.2923040.
[68] Traiola M, Virazel A, Girard P, Barbareschi M, Bosio A. Maximizing yield for approximate integrated circuits. In Proc. the 2020 Design, Automation & Test in Europe Conference & Exhibition, Mar. 2020, pp.810–815. DOI: 10.23919/DATE48585.2020.9116341.
[69] Sierawski B D, Bhuva B L, Massengill L W. Reducing soft error rate in logic circuits through approximate logic functions. IEEE Trans. Nuclear Science, 2006, 53(6): 3417–3421. DOI: 10.1109/TNS.2006.884352.
[70] Sánchez-Clemente A, Entrena L, García-Valderas M, López-Ongil C. Logic masking for SET mitigation using approximate logic circuits. In Proc. the 18th IEEE International On-Line Testing Symposium, Jun. 2012, pp.176–181. DOI: 10.1109/IOLTS.2012.6313868.
[71] Gomes I A C, Martins M, Kastensmidt F L, Reis A, Ribas R, Novalès S P. Methodology for achieving best trade-off of area and fault masking coverage in ATMR. In Proc. the 15th Latin American Test Workshop-LATW, Mar. 2014. DOI: 10.1109/LATW.2014.6841916.
[72] Gomes I A C, Martins M, Reis A, Kastensmidt F L. Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. In Proc. the 16th Latin-American Test Symposium, Mar. 2015. DOI: 10.1109/LATW.2015.7102522.
[73] Deveautour B, Traiola M, Virazel A, Girard P. QAMR: An approximation-based fully reliable TMR alternative for area overhead reduction. In Proc. the 2020 IEEE European Test Symposium, May 2020. DOI: 10.1109/ETS48528.2020.9131574.
[74] Deveautour B, Traiola M, Virazel A, Girard P. Reducing overprovision of triple modular reduncancy owing to approximate computing. In Proc. the 27th IEEE International Symposium on On-Line Testing and Robust System Design, Jun. 2021. DOI: 10.1109/IOLTS52814.2021.9486699.
[75] Masadeh M, Aoun A, Hasan O, Tahar S. Highly-reliable approximate quadruple modular redundancy with approximation-aware voting. In Proc. the 32nd International Conference on Microelectronics, Dec. 2020. DOI: 10.1109/ICM50269.2020.9331771.
[1] Ying Zhang, Peng-Fei Ji, Pan-Wei Zhu, Zebo Peng, Hua-Wei Li, and Jian-Hui Jiang. Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip [J]. Journal of Computer Science and Technology, 2023, 38(2): 405-421.
[2] Wen-Jun Tang, Rong Chen, Jia-Li Zhang, Lin Huang, Sheng-Jie Zheng, and Shi-Kai Guo. Optimization of Web Service Testing Task Assignment in Crowdtesting Environment [J]. Journal of Computer Science and Technology, 2023, 38(2): 455-470.
[3] Yu-Qin Dou and Cheng-Hua Wang. An Optimization Technique for PMF Estimation in Approximate Circuits [J]. Journal of Computer Science and Technology, 2023, 38(2): 289-297.
[4] Bo Yi, Xing-Wei Wang, Min Huang, and Qiang He. A QoS Based Reliable Routing Mechanism for Service Customization [J]. Journal of Computer Science and Technology, 2022, 37(6): 1492-1508.
[5] Jia-Ming Zhang, Zhan-Qi Cui, Xiang Chen, Huan-Huan Wu, Li-Wei Zheng, and Jian-Bin Liu. DeltaFuzz: Historical Version Information Guided Fuzz Testing [J]. Journal of Computer Science and Technology, 2022, 37(1): 29-49.
[6] Ze-Lin Zhao, Di Huang, and Xiao-Xing Ma. TOAST: Automated Testing of Object Transformers in Dynamic Software Updates [J]. Journal of Computer Science and Technology, 2022, 37(1): 50-66.
[7] Jin-Chi Chen, Yi Qin, Hui-Yan Wang, and Chang Xu. Simulation Might Change Your Results: A Comparison of Context-Aware System Input Validation in Simulated and Physical Environments [J]. Journal of Computer Science and Technology, 2022, 37(1): 83-105.
[8] Jiao-Yun Yang, Jun-Da Wang, Yi-Fang Zhang, Wen-Juan Cheng, Lian Li. A Heuristic Sampling Method for Maintaining the Probability Distribution [J]. Journal of Computer Science and Technology, 2021, 36(4): 896-909.
[9] Yi-Sen Xu, Xiang-Yang Jia, Fan Wu, Lingbo Li, Ji-Feng Xuan. Automatically Identifying Calling-Prone Higher-Order Functions of Scala Programs to Assist Testers [J]. Journal of Computer Science and Technology, 2020, 35(6): 1278-1294.
[10] Jie Xiao, Zhan-Hui Shi, Jian-Hui Jiang, Xu-Hua Yang, Yu-Jiao Huang, Hai-Gen Hu. A Locating Method for Reliability-Critical Gates with a Parallel-Structured Genetic Algorithm [J]. Journal of Computer Science and Technology, 2019, 34(5): 1136-1151.
[11] Ming-Zhe Zhang, Yun-Zhan Gong, Ya-Wen Wang, Da-Hai Jin. Unit Test Data Generation for C Using Rule-Directed Symbolic Execution [J]. Journal of Computer Science and Technology, 2019, 34(3): 670-689.
[12] Bo Guo, Young-Woo Kwon, Myoungkyu Song. Decomposing Composite Changes for Code Review and Regression Test Selection in Evolving Software [J]. Journal of Computer Science and Technology, 2019, 34(2): 416-436.
[13] Xu-Zhou Zhang, Yun-Zhan Gong, Ya-Wen Wang, Ying Xing, Ming-Zhe Zhang. Automated String Constraints Solving for Programs Containing String Manipulation Functions [J]. , 2017, 32(6): 1125-1135.
[14] Xiao-Fang Qi, Zi-Yuan Wang, Jun-Qiang Mao, Peng Wang. Automated Testing of Web Applications Using Combinatorial Strategies [J]. , 2017, 32(1): 199-210.
[15] Ju Qian, Di Zhou. Prioritizing Test Cases for Memory Leaks in Android Applications [J]. , 2016, 31(5): 869-882.
Viewed
Full text


Abstract

Cited
  Shared   
  Discussed   
[1] Li Wei;. A Structural Operational Semantics for an Edison Like Language(2)[J]. , 1986, 1(2): 42 -53 .
[2] Liu Mingye; Hong Enyu;. Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems[J]. , 1986, 1(2): 83 -92 .
[3] Wang Xuan; Lü Zhimin; Tang Yuhai; Xiang Yang;. A High Resolution Chinese Character Generator[J]. , 1986, 1(2): 1 -14 .
[4] C.Y.Chung; H.R.Hwa;. A Chinese Information Processing System[J]. , 1986, 1(2): 15 -24 .
[5] Sun Zhongxiu; Shang Lujun;. DMODULA:A Distributed Programming Language[J]. , 1986, 1(2): 25 -31 .
[6] Chen Shihua;. On the Structure of (Weak) Inverses of an (Weakly) Invertible Finite Automaton[J]. , 1986, 1(3): 92 -100 .
[7] Zhang Cui; Zhao Qinping; Xu Jiafu;. Kernel Language KLND[J]. , 1986, 1(3): 65 -79 .
[8] Huang Heyan;. A Parallel Implementation Model of HPARLOG[J]. , 1986, 1(4): 27 -38 .
[9] Zheng Guoliang; Li Hui;. The Design and Implementation of the Syntax-Directed Editor Generator(SEG)[J]. , 1986, 1(4): 39 -48 .
[10] Shen Li; Stephen Y.H.Su;. Generalized Parallel Signature Analyzers with External Exclusive-OR Gates[J]. , 1986, 1(4): 49 -61 .

ISSN 1000-9000(Print)

         1860-4749(Online)
CN 11-2296/TP

 Home
Editorial Board
Author Guidelines
Subscription		 Journal of Computer Science and Technology
Institute of Computing Technology, Chinese Academy of Sciences
P.O. Box 2704, Beijing 100190 P.R. China
Tel.:86-10-62610746
E-mail: jcst@ict.ac.cn
 
  Copyright ©2015 JCST, All Rights Reserved