Journal of Computer Science and Technology ›› 1986, Vol. 1 ›› Issue (1): 26-34.

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Design of a Vector Processor

Lin Qi   

  1. Institute of Computing Technology, Academia Sinica, Beijing, China
  • Received:1984-12-25 Online:1986-01-10 Published:2022-01-20

This paper discusses the inherent parallelism limits on several applications for vector computers, the parallel capabilities of several architectures and two ways (traditional instruction control flow and data control flow) by which the capabilities can be used. Then a scheme for a pipelined vector processor of multi-processing units is presented. The basic system structure and its function on highly sparse vector processing are described. A vector cache system and a distributed main memory are also considered, which are intended to sustain extremely high access rates for the processor. A microprocessor based vector processor is constructed, which can simulate the high performance version of the processor.



[1] I.S. Duff and J.K. Reid, Experience of Sparse Matrix Codes on the CRAY-1,Computer Physics Communications,26 (1982).
[2] CDC CYBER 200 Model 205 Computer System Hardware Reference Manual, Control Data Corporation, 1981.
[3] CRAY-1 Computer System Reference Manual, Cray Research Inc., Minneapolis, 1976.
[4] Alan Jay Smith, Cache Memories,Computer Surveys,14:3(1982), 473–530.
[5] The CRAY X-MP Series, Publication No. MP-0001, Cray Research Inc., 1982.
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ISSN 1000-9000(Print)

         1860-4749(Online)
CN 11-2296/TP

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