Some Covering Problems and Their Solutions in Automatic Logic Synthesis Systems

This paper describes the partitioning of the set of the Boolean equations generated by the hardware logic translator and the conversion of the subsets into cube arrays. Subsequent to this,it is aimed:(1)to find out the minimal sets of input variables;(2)to finish the logic minimization;and(3)to decompose a large logic array into smaller ones to meet the design constraints if necessary. These three problems cart all be reduced to solving the corresponding covering problems,which may have considerable scales....