• Articles • Previous Articles     Next Articles

On GID-Testable Two-Dimensional Iterative Arrays

Huang WeiKang; F.Lombard;   

  1. Dept.of Electrical Engineering; Fudan Univereity; Shanghai 200433; Dept.of Computer Science; Texas A&M Universitg; College Station; Texas 77843-3112; USA;
  • Online:1994-01-10 Published:1994-01-10

A new approach is presented for easily testable two-dimensional iterative arrays.It is an improvment on GI-testability (Group Identical testability) and is referred to as GID-testability (Group Identical and Different testability). In a GID-testable twodimensional array, the primary x and y outputs are organized into groups and every group has more than one output. This is similar to the GI-testable arrays. However,GID-testability not only ensures that identical test responses can be obtained from every out…

Key words: lower bound estimation; chaining; pipelining; mutual exclusion; high-level synthesis;



[1] Sridhar T, Hayes J P. A functional approach to testing bit-sliced microprocessors. IEEE Trans.on Comput, 1981, C-30(8): 563-670.

[2] Sridhar T, Hayes J P. Design of easily-testable bit-sliced systems. IEEE Trans.on Comput, 1981, C-30(11): 842-854.

[3] Friedman A D. Easily testable iterative arrays. IEEE Trans.on Comput, 1976, C-25(6): 605-613. ……….
[1] Lan Huang, Da-Lin Li, Kang-Ping Wang, Teng Gao, Adriano Tavares. A Survey on Performance Optimization of High-Level Synthesis Tools [J]. Journal of Computer Science and Technology, 2020, 35(3): 697-720.
[2] Yong Guan (关永) and Jingling Xue (薛京灵), Senior Member, IEEE, Member, ACM. Leakage-Aware Modulo Scheduling for Embedded VLIW Processors [J]. , 2011, 26(3): 405-417.
[3] Yi-Song Wang, Member, CCF, Ming-Yi Zhang, Member, CCF, and Jia-Huai You. Logic Programs, Compatibility and Forward Chaining Construction [J]. , 2009, 24(6): 1125-1137.
[4] Awadhesh Kumar Singh and Anup Kumar Bandyopadhyay. Verifying Mutual Exclusion and Liveness Properties with Split Preconditions [J]. , 2004, 19(6): 0-0.
[5] Tun Li, Yang Guo, and Si-Kun Li. Automatic Circuit Extractor for HDL Description Using Program Slicing [J]. , 2004, 19(5): 0-0.
[6] Heng Hu, Hong-Xi Xue, and Ji-Nian Bian. HSM2: A New Heuristic State Minimization Algorithm for Finite State Machine [J]. , 2004, 19(5): 0-0.
[7] Lifeng He, Yuyan Chao and Hidenori Itoh. Eliminating Redundant Search Space on Backtracking for Forward Chaining Theorem Proving [J]. , 2003, 18(5): 0-0.
[8] HE LiFeng (何立风), Yuyan Chao, Tsuyoshi Nakamura and Hidenori Itoh. Z-SATCHMORE: An Improvement of A-SATCHMORE [J]. , 2003, 18(2): 0-0.
[9] Shen Zhaoxuan and Jong Ching Chuen. Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis [J]. , 2002, 17(6): 0-0.
[10] LI Xiaowei; Paul Y.S. Cheung;. High Level Synthesis for Loop-Based BIST [J]. , 2000, 15(4): 338-345.
[11] LI Xiaowei(李晓维)and Paul Y.S.Cheung(张英相). High Level Synthesis for Loop-Based BIST [J]. , 2000, 15(4): 0-0.
[12] Yan Zongfu; Liu Mingye;. The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT [J]. , 1996, 11(6): 562-569.
[13] Wang Jian; Andreas Krall; M.Anton Ertl;. Trace Software Pipelining [J]. , 1995, 10(6): 481-490.
[14] Kian-Lee Tan;. Optimization of Multi-Join Queries in Shared-Nothing Systems [J]. , 1995, 10(2): 149-162.
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed   
No Suggested Reading articles found!

ISSN 1000-9000(Print)

         1860-4749(Online)
CN 11-2296/TP

Home
Editorial Board
Author Guidelines
Subscription
Journal of Computer Science and Technology
Institute of Computing Technology, Chinese Academy of Sciences
P.O. Box 2704, Beijing 100190 P.R. China
Tel.:86-10-62610746
E-mail: jcst@ict.ac.cn
 
  Copyright ©2015 JCST, All Rights Reserved