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Accelerated Techniques in Stem Fault Simulation

Shi Yin; Wei Daozheng;   

  1. CAD Laboratory; Institute of Computing Technology; Chinese Academy of SciencesBeijing 100080;
  • Online:1996-11-10 Published:1996-11-10

In order to cope with the most expensive stem fault simulation in fault simu-lation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques,the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental resu…

Key words: reduct; attribute order; rough set; VHDL simulator; event-driven algorithm; cycle-based algorithm; levelization;



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ISSN 1000-9000(Print)

         1860-4749(Online)
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