Single-Cycle Bit Permutations with MOMR Execution

Secure computing paradigms impose new architectural challenges forgeneral-purpose processors. Cryptographic processing is needed forsecure communications, storage, and computations. We identify twocategories of operations in symmetric-key and public-key cryptographicalgorithms that are not common in previous general-purpose workloads:advanced bit operations within a word and multi-word operations. Wedefine MOMR (Multiple Operands Multiple Results) execution ordatarich execution as a unified solution to both challenges. Itallows arbitrary n-bit permutations to be achieved in one or twocycles, rather than O(n) cycles as in existing RISC processors. Italso enables significant acceleration of multi-word multiplicationsneeded by public-key ciphers. We propose two implementations of MOMR:one employs only hardware changes while the other uses Instruction SetArchitecture (ISA) support. We show that MOMR execution leveragesavailable resources in typical multi-issue processors with minimaladditional cost. Multi-issue processors enhanced with MOMR units provideadditional speedup over standard multi-issue processors with the samedatapath. MOMR is a general architectural solution for word-orientedprocessor architectures to incorporate datarich operations.