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Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18$\mu$m CMOS[J]. Journal of Computer Science and Technology, 2007, 22(1): 25-27.
Citation:
Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18$\mu$m CMOS[J]. Journal of Computer Science and Technology, 2007, 22(1): 25-27.
Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18$\mu$m CMOS[J]. Journal of Computer Science and Technology, 2007, 22(1): 25-27.
Citation:
Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang. A 485ps 64-Bit Parallel Adder in 0.18$\mu$m CMOS[J]. Journal of Computer Science and Technology, 2007, 22(1): 25-27.
This paper presents an optimized 64-bit parallel adder.Sparse-tree architecture enables low carry-merge fan-outs andinter-stage wiring complexity. Single-rail and semi-dynamic circuitimproves operation speed. Simulation results show that the proposedadder can operate at 485ps with power of 25.6mW in 0.18\mum CMOS process.It achieves the goal of higher speed and lower power.
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