Chip Multithreaded Consistency Model

Multithreaded technique is the developing trend ofhigh performance processor. Memory consistency model isessential to the correctness, performance and complexity ofmultithreaded processor. The chip multithreaded consistency modeladapting to multithreaded processor is proposed in this paper. Therestriction imposed on memory event ordering by chip multithreadedconsistency is presented and formalized. With the idea of criticalcycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistencymodel satisfies the criterion of correct execution of sequentialconsistency model. Chip multithreaded consistency model provides a wayof achieving high performance compared with sequential consistencymodel and ensures the compatibility of software that the executionresult in multithreaded processor is the same as the execution resultin uniprocessor. The implementation strategy of chip multithreadedconsistency model in Godson-2 SMT processor is also proposed. Godson-2SMT processor supports chip multithreaded consistency model correctlyby exception scheme based on the sequential memory access queue of eachthread.