Special Issue: Computer Architecture and Systems

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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

Da Wang1, 2, Yu Hu1, Hua-Wei Li1, and Xiao-Wei Li1,*   

  1. 1Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China 2Graduate University of Chinese Academy of Sciences, Beijing 100049, China
  • Received:2008-05-17 Revised:2008-09-01 Online:2008-11-10 Published:2008-11-10

This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test (BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops (PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation (ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing (HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.


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