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›› 2009, Vol. 24 ›› Issue (6): 1061-1073.

Special Issue: Computer Architecture and Systems

• Special Section on International Partnership Programs Supported by CAS •

### Godson-T: An Efficient Many-Core Architecture for Parallel Program Executions

Dong-Rui Fan* (范东睿), Member, CCF, IEEE, Nan Yuan (袁楠), Jun-Chao Zhang (张军超), Member, CCF, ACM, Yong-Bin Zhou (周永彬), Wei Lin (林伟), Feng-Long Song (宋风龙), Xiao-Chun Ye (叶笑春), He Huang (黄河), Lei Yu (余磊), Guo-Ping Long (龙国平), Hao Zhang (张浩), and Lei Liu (刘磊)

1. Key Laboratory of Computer Systems and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
• Received:2009-03-13 Revised:2009-09-28 Online:2009-11-05 Published:2009-11-05
• About author:
Dong-Rui Fan graduated from the Department of Mathematical Science at Beijing Jiaotong University with a Bachelor's degree in 2000, and he received the Ph.D. degree from Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) in 2005. Now, he is an associate researcher at ICT, a member of CCF and IEEE. He worked together with members of AMS (Advanced Micro-System) research group and designed the new processing models --- Godson-X and Godson-T. Currently, His research interest focuses on many-core system, including the design of microarchitecture, parallel processing, and runtime system.
Nan Yuan graduated from the Department of Computer Science and Technology at Beijing University of Posts and Telecommunication with a Bachelor's degree in 2004, and he is currently a Ph.D. candidate of ICT, CAS. His current research interests include parallel architecture design and runtime system design.
Jun-Chao Zhang is currently an engineer at ICT, CAS. He received his Ph.D. degree in computer science from ICT, CAS in 2005 and his B.Eng. degree from Xi'an Jiaotong University in 1999. His research interests include computer architecture, parallel computing, compiler and parallel languages. He is an ACM member and CCF member.
Yong-Bin Zhou received his B.Eng. degree from University of Science and Technology of China (USTC). Currently, he is a Ph.D. candidate in computer science at ICT, CAS. His recent research topics include computer architecture and parallel computing.
Wei Lin received his B.Sc. degree from Tianjin University. Currently, he is a Ph.D. candidate in computer science at ICT, CAS. His research interests include computer architecture, parallel computing, and operating system.
Feng-Long Song graduated from the Department of Management and Economics at Shandong Normal University and received Master's degree in 2006. He is a Ph.D. candidate of ICT, CAS. His research interests focus on high performance computer architecture, on-chip memory hierarchy, and parallel computing.
Xiao-Chun Ye received his B.Sc. degree from Beijing Normal University in 2004. Currently, he is a Ph.D. candidate in computer science at ICT, CAS. His recent research topics include computer architecture, parallel computing, and bioinformatics.
He Huang is a Ph.D. candidate at ICT, CAS. His research interests include processor micro-architecture, operating system and VLSI backend design.
Lei Yu is currently a Ph.D. candidate at ICT, CAS. His current research interests include computer architecture and parallel computing.
Guo-Ping Long is currently a Ph.D. candidate at ICT, CAS. His research interests include parallel programming, performance modeling and evaluation.
Hao Zhang is an assistant researcher at ICT, CAS. Zhang received the Ph.D. degree in computer science from ICT in 2008. His research interests include design, analysis, implementation, and benchmarking of processor architectures|switching and routing of on chip networks|and high throughput memory system.
Lei Liu received his B.Sc. degree from Peking University in 2004. Currently he is a Ph.D. candidate at ICT, CAS. His research topic is power management of many-core architecture.
• Supported by:

Supported by the National Basic Research 973 Program of China under Grant No. 2005CB321600, the National High-Tech Research and Development 863 Program of China under Grant No. 2009AA01Z103, the National Natural Science Foundation of China under Grant No. 60736012, the National Science Fund for Distinguished Young Scholars under Grant No. 60925009, and the Beijing Natural Science Foundation under Grant No. 4092044.

Moore's law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson-T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreads-like programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

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