›› 2010, Vol. 25 ›› Issue (2): 257-266.

Special Issue: Computer Architecture and Systems; Computer Networks and Distributed Computing

• Special Section on CPU Researches in China • Previous Articles     Next Articles

CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors

Jing-Lei Wang1 (王惊雷), Yi-Bo Xue2 (薛一波), Member, CCF, IEEE, Hai-Xia Wang2 (王海霞), Member, CCF, IEEE, Chong-Min Li1 (李崇民), and Dong-Sheng Wang1, 2 (汪东升), Senior Member, CCF, Member, IEEE   

  1. 1Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
    2Tsinghua National Laboratory of Information Science and Technology, Beijing 100084, China
  • Received:2009-02-12 Revised:2010-01-24 Online:2010-03-05 Published:2010-03-05
  • About author:
    Jing-Lei Wang received his B.S. degree from Zhejiang University, and M.S. degree from Tsinghua University. His research interests include high performance computing, chip multiprocessor architecture.
    Yi-Bo Xue received his B.S. and M.S. degrees from Harbin Institute of Technology, and Ph.D. degree from Chinese Academy of Sciences. He is a professor of Tsinghua University, member of CCF and IEEE. His research interests include high performance computing, parallel processing and network security.
    Hai-Xia Wang received her B.S. degree from Nankai University, and Ph.D. degree from Chinese Academy of Sciences. She is an associate professor of Tsinghua University, member of CCF and IEEE. Her research interests include high performance computing, chip multiprocessor architecture and formal check.
    Chong-Min Li received his B.S. and M.S. degrees from Daqing Petroleum Institute and Tsinghua University respectively. His research interests include high performance computing, chip multiprocessor architecture.
    Dong-Sheng Wang received his B.S. and Ph.D. degrees from Harbin Institute of Technology. He is a professor of Tsinghua University. He is a senior member of China Computer Federation, member of IEEE. His research interests include computer architecture, high performance computing, storage & file systems, and network security.
  • Supported by:

    This work is supported by the National Natural Science Foundation of China under Grant Nos. 60970002, 60833004, 60773146, and 60673145.

As the number of cores in chip multiprocessors (CMPs) increases, cache coherence protocol has become a key issue in integration of chip multiprocessors. Supporting cache coherence protocol in large chip multiprocessors still faces three hurdles: design complexity, performance and scalability. This paper proposes Cache Coherent Network on Chip (CCNoC), a scheme that decouples cache coherency maintenance from processors and shared L2 caches and implements it completely in network on chip to free up processors and shared L2 caches from the chore of maintaining coherency, thereby reduces design complexity of CMPs. In this way, CCNoC also improves the performance of cache coherence protocol through reducing directory access latency and enhances scalability by avoiding massive directories overhead in shared L2 caches. In CCNoC, coherence state caches and active directory caches are implemented in the network interface components of network on chip to maintain cache coherence states for blocks in L1 caches and manage directory information for recently accessed blocks in L2 caches respectively. CCNoC provides a scalable CMP framework to tackle cache coherency which is the foundation of CMP. This paper evaluates the performance of CCNoC. Experimental results show that for a 16-core system, CCNoC improves performance by 3% on average over the conventional chip multiprocessor and by 10% at best, while reduces storage overhead by 1.8% and saves directory storage by 88%, showing good scalability.


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