›› 2010, Vol. 25 ›› Issue (2): 267-273.

• Special Section on CPU Researches in China • Previous Articles     Next Articles

Design and Application of Instruction Set Simulator on Multi-Core Verification

Xiang-Dong Hu (胡向东), Senior Member, CCF, Yong Guo (郭勇), Ying Zhu (朱英), Xin Guo (郭昕), and Peng Wang (王鹏)   

  1. National High Performance IC (Shanghai) Design Center, Shanghai 201204, China
  • Received:2009-03-23 Revised:2010-01-25 Online:2010-03-05 Published:2010-03-05
  • About author:
    Xiang-Dong Hu is a processor in National High Performance IC (Shanghai) Design Center. He is a senior member of China Computer Federation (CCF). He received his B.S. and M.S. degrees in electrical engineering from Zhejiang University. His main research interests include high performance computer architecture, and high performance processor design & verification.
    Yong Guo is an assistant processor in National High Performance IC (Shanghai) Design Center. His research interests include simulation, verification, and compiler optimization.
    Ying Zhu is a processor in National High Performance IC (Shanghai) Design Center. Her research interests include high performance processor design & verification, and hardware design.
    Xin Guo is an associate processor in National High Performance IC (Shanghai) Design Center. Her research interests include high performance processor design, and hardware design.
    Peng Wang is an assistant processor in National High Performance IC (Shanghai) Design Center. He received the Ph.D. degree from Tsinghua University. His research interests include high performance processor design.

Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi-core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the ``save and restore'' mechanism, the verification procedure and the debugging are speeding up greatly.


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