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Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu, Bao-Xia Fan. A Robust and Power-Efficient SoC Implementation in 65nm[J]. Journal of Computer Science and Technology, 2013, 28(4): 682-688. DOI: 10.1007/s11390-013-1368-7
Citation: Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu, Bao-Xia Fan. A Robust and Power-Efficient SoC Implementation in 65nm[J]. Journal of Computer Science and Technology, 2013, 28(4): 682-688. DOI: 10.1007/s11390-013-1368-7

A Robust and Power-Efficient SoC Implementation in 65nm

  • Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.
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