Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability (DFT)features and low-cost testing solutions of a general purposemicroprocessor. The optimized DFT features are presented in detail. Ahybrid scan compression structure was executed and achieved compressionratio more than ten times. Memory built-in self-test (BIST)circuitries were designed with scan collars instead of bitmaps to reducearea overheads and to improve test and debug efficiency. The implementedDFT framework also utilized internal phase-locked loops (PLL) toprovide complex at-speed test clock sequences. Since there are stilllimitations in this DFT design, the test strategies for this case arequite complex, with complicated automatic test pattern generation(ATPG) and debugging flow. The sample testing results are given in thepaper. All the DFT methods discussed in the paper are prototypes for ahigh-volume manufacturing (HVM) DFT plan to meet high quality testgoals as well as slow test power consumption and cost.