›› 2013, Vol. 28 ›› Issue (4): 671-681.doi: 10.1007/s11390-013-1367-8

Special Issue: Computer Architecture and Systems

• Architecture and VLSI Design • Previous Articles     Next Articles

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

Ning Xu1 (徐宁), Senior Member, CCF, Yu-Chun Ma2,3,* (马昱春), Jia Liu1,2 (刘佳) and Shou-Chun Tao1,2 (陶守春)   

  1. 1. School of Computer Science and Technology, Wuhan University of Technology, Wuhan 430070, China;
    2. Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China;
    3. Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, China
  • Received:2012-07-16 Revised:2013-02-07 Online:2013-07-05 Published:2013-07-05
  • Supported by:

    This work is supported by the National Natural Science Foundation of China under Grant No. 61076035 and TNList Cross-discipline Foundation of Tsinghua University, China.

To reduce the interconnect delay and improve the chip performance, three-dimensional (3D) chip emerged with the rapid increasing of chip integration and chip power density. Therefore, thermal issue is one of the critical challenges in 3D IC design due to the high power density. Multiple Supply Voltages (MSV) technique provides an efficient way to optimize power consumption which in turn may alleviate the hotspots. But the voltage assignment is limited not only by the performance constraints of the design, but also by the physical layout of circuit modules since the modules with the same voltage should be gathered to reduce the power-network routing resource. Especially in 3D designs, the optimization using MSV technique becomes even more complicated since the high temperature also influences the power consumption and delay on paths. In this paper, we address the voltage-island generation problem for MSV designs in 3D ICs based on a mixed integer linear programming (MILP) model. First, we propose a general MILP formulation for voltage-island generation to optimize thermal distribution as well as power-network routing resources while maintaining the whole chip performance. With the thermal-power interdependency, an iterative optimization approach is proposed to obtain the convergence. Experimental results show that our thermal-aware voltage-island generation approach can reduce the maximal on-chip temperature by 23.64% with a reasonable runtime and save the power-network routing resources by 16.71%.

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