›› 2014, Vol. 29 ›› Issue (2): 273-280.doi: 10.1007/s11390-014-1429-6

Special Issue: Computer Architecture and Systems

• Special Section on Cloud-Sea Computing Systems • Previous Articles     Next Articles

Reinventing Memory System Design for Many-Accelerator Architecture

Ying Wang1, 2 (王颖), Student Member, CCF, ACM, IEEE, Lei Zhang1 (张磊), Member, CCF, ACM, IEEE Yin-He Han1, * (韩银和), Member, CCF, ACM, IEEE and Hua-Wei Li1 (李华伟), Senior Member, CCF, IEEE, Member, ACM   

  1. 1 State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2 University of Chinese Academy of Sciences, Beijing 100049, China
  • Received:2013-11-19 Revised:2014-01-21 Online:2014-03-05 Published:2014-03-05
  • About author:Ying Wang received the B.S. and M.S. degrees in electrical engineering from Harbin Institute of Technology, in 2007 and 2009, respectively. He is currently a Ph.D. candidate at Institute of Computing (ICT), Chinese Academy of Sciences (CAS), Beijing. His research interests include reconfigurable computing, interconnects, memory system and fault-tolerance for many-core architectures.
  • Supported by:

    Supported by the National Natural Science Foundation of China under Grant Nos. 61173006, 60921002, the National Basic Research 973 Program of China under Grant No. 2011CB302503, and the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No. XDA06010403.

The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units (FUs), becomes a great alternative to homogeneous chip multiprocessors (CMPs) for its superior power-effciency. However, the emerging many-accelerator processor shows a much more complicated memory accessing pattern than general purpose processors (GPPs) because the abundant on-chip FUs tend to generate highly-concurrent memory streams with distinct locality and bandwidth demand. The disordered memory streams issued by diverse accelerators exhibit a mutual-interference behavior and cannot be effciently handled by the orthodox main memory interface that provides an inflexible data fetching mode. Unlike the traditional DRAM memory, our proposed Aggregation Memory System (AMS) can function adaptively to the characterized memory streams from different FUs, because it provides the FUs with different data fetching sizes and protects their locality in memory access by intelligently interleaving their data to memory devices through sub-rank binding. Moreover, AMS can batch the requests without sub-rank conflict into a read burst with our optimized memory scheduling policy. Experimental results from trace-based simulation show both conspicuous performance boost and energy saving brought by AMS.

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