Journal of Computer Science and Technology ›› 2020, Vol. 35 ›› Issue (2): 468-474.doi: 10.1007/s11390-020-9688-x

• Special Section of ChinaSys 2019 • Previous Articles     Next Articles

A Machine Learning Framework with Feature Selection for Floorplan Acceleration in IC Physical Design

Shu-Zheng Zhang, Zhen-Yu Zhao*, Chao-Chao Feng, Lei Wang        

  1. College of Computer Science and Technology, National University of Defense Technology, Changsha 410003, China
  • Received:2019-05-22 Revised:2019-08-29 Online:2020-03-05 Published:2020-03-18
  • Contact: Zhen-Yu Zhao
  • About author:Shu-Zheng Zhang is currently a Master student in the College of Computer Science and Technology, National University of Defense Technology, Changsha. He received his B.Sc. degree in electronical information science and technology from Harbin Institute of Technology, Harbin, in 2017. His current research interests include high-performance microprocessor design and machine learning.
  • Supported by:
    This work was supported by the HeGaoJi Program of China under Grant Nos. 2018ZX01029103 and 2017ZX01038104-002, and the National Natural Science Foundation of China under Grant Nos. 61802427 and 61902408.

Floorplan is an important process whose quality determines the timing closure in integrated circuit (IC) physical design. And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration. Applying machine learning to the floorplan stage is a potential method to accelerate the floorplan iteration. However, there exist two challenges which are selecting proper features and achieving a satisfying model accuracy. In this paper, we propose a machine learning framework for floorplan acceleration with feature selection and model stacking to cope with the challenges, targeting to reduce time and effort in integrated circuit physical design. Specifically, the proposed framework supports predicting post-route slack of static random-access memory (SRAM) in the early floorplan stage. Firstly, we introduce a feature selection method to rank and select important features. Considering both feature importance and model accuracy, we reduce the number of features from 27 to 15 (44% reduction), which can simplify the dataset and help educate novice designers. Then, we build a stacking model by combining different kinds of models to improve accuracy. In 28 nm technology, we achieve the mean absolute error of slacks less than 23.03 ps and effectively accelerate the floorplan process by reducing evaluation time from 8 hours to less than 60 seconds. Based on our proposed framework, we can do design space exploration for thousands of locations of SRAM instances in few seconds, much more quickly than the traditional approach. In practical application, we improve the slacks of SRAMs more than 75.5 ps (177% improvement) on average than the initial design.

Key words: physical design; machine learning; feature selection; design space exploration;

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