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Exploiting Deterministic TPG for Path Delay Testing

LI Xiaowei; Paul Y.S. Cheung;   

  1. Department of Computer Science; Peking University; Beijing 100871; P.R.China; Department of Electrical and Electronic Engineering; The University of Hong Kong Pokfulam Road; Hong Kong; P.R. China;
  • Online:2000-09-10 Published:2000-09-10

Detection of path delay faults requires two-pattern tests. BIST technique provides a low-cost test solution. This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for path delay testing. Given a set of pre-generated test-pairs with pre-determined fault coverage, a deterministic TPG is synthesized to apply the given test-pair set in a limited test time. To achieve this objective, configurable linear feedback shift register (LFSR) structures are used. Techniq…

Key words: type system,type inference,type-checking,type theory,semantic model;

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[2] Pilarski S, Pierzyriska A. BIST and delay fault detection. In Proc. IEEE Int. Test Conf. (ITC'93), 1993, pp.236-242.

[3] Furuya K, McClusky E J. Two-pattern test capability of autonomous TPG circuits. In Proc. IEEE Int. Test Conf (ITC'91), 1991, pp.704-711. ……….
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