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CN 11-2296/TP
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  • Table of Content
      10 April 1990, Volume 5 Issue 2 Previous Issue    Next Issue
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    Guest Editor s Introduction:Fault-Tolerant Computing
    Min Yinghua;
    Journal of Computer Science and Technology, 1990, 5 (2): 3-4. 
    Abstract   PDF(94KB) ( 1107 )   Chinese Summary
    This is the first special issue of the Journal of Computer Science and Technology onFault-Tolerant Computing.Fault-Tolerant Computing,characterized as the ability ofexecuting specified algorithms in a satisfactory fashion in the presence of hardware fail-ures and software errors,was emerged in the 1970's and has become an important disci-pline in the field of computer science and technology.
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    DFTSNA:A Distributed Fault-Tolerant Shipboard System
    Xu Jie; Li Qingnan; Huang Shize; Xu Jiangfeng;
    Journal of Computer Science and Technology, 1990, 5 (2): 109-116. 
    Abstract   PDF(370KB) ( 1213 )   Chinese Summary
    This paper describes the architecture,fundamental principle and implementation of a distributed fault-tolerant system——DFTSNA.Its objective is to combine extreme reliability with high availability in a shipboard environment.Multi-level fault tolerance is considered and several special-purpose hardware subsystems(F-T clusters)are developed.The physical and functional distribution of the system is empha- sized to meet the stringent shipboard requirements.A number of algorithms are produced to support fault-to…
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    A Reliable and Fault-Tolerant Interconnection Network
    Deng Yaping; Chen Tinghuai;
    Journal of Computer Science and Technology, 1990, 5 (2): 117-126. 
    Abstract   PDF(247KB) ( 1106 )   Chinese Summary
    An interconnection network with multistage redundant paths is introduced for using in high-perform- ance multiprocessor systems.The routing algorithm of the proposed network is simple and dynamically reroutable.The analysis of the fault-tolerance and performance of the network are given.It is shown that the probability of acceptance and the performance-to-cost ratio of the network are better than those of F and Gamma Networks.Another advantages of the proposed network is the smaller amount of interstage lin…
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    A Distributed Error Recovery Technique and Its Implementation and Application on UNIX
    Zhou Di; Xu Xiangwen;
    Journal of Computer Science and Technology, 1990, 5 (2): 127-138. 
    Abstract   PDF(541KB) ( 1196 )   Chinese Summary
    This paper presents a checkpoint setting technique to eliminate domino effect in backward recovery in distributed systems,which is very efficient,powerful,widely applicable and easy to be implememted.Besides theoretical analysis,an implementation on UNIX system and a package for software fault-tolerance are in- troduced.Then the problems of checkpoint management and process termination are discussed.
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    PROM:A Support for Robust Replication in a Distributed Object Environment
    A.Corradi; L.Leonardi;
    Journal of Computer Science and Technology, 1990, 5 (2): 139-155. 
    Abstract   PDF(412KB) ( 1050 )   Chinese Summary
    The concept of object can be employed to achieve tolerance to hardware faults in distributed systems.Replication by introducing several copies for each object allows a continuous service even in case of failure.In particular,the paper describes an object model,PROM,which exploits replication by defining sev- eral passive back-up copies for any object.The system automatically recovers any failure of a copy in execu- tion by activating a spare copy and restarting it from a previous checkpoint. The aim of the …
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    Parallel Critical Path Tracing——A Fault Simulation Algorithm for Combinational Circuits
    Wei Daozheng;
    Journal of Computer Science and Technology, 1990, 5 (2): 156-163. 
    Abstract   PDF(181KB) ( 1108 )   Chinese Summary
    Critical path tracing,a fault simulation method for gate-level combinational circuits,is extended to the parallel critical path tracing for functional block-level combinational circuits.If the word length of the host computer is m,then the parallel critical path tracing will be approximately m times faster than the original one.
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    Product-Oriented Test-Pattern Generation for Programmable Logic Arrays
    Li Jintao; Min Yinghua;
    Journal of Computer Science and Technology, 1990, 5 (2): 164-174. 
    Abstract   PDF(502KB) ( 1185 )   Chinese Summary
    A Product-oriented test-pattern generation strategy for Programmable Logic Arrays(PLAs)is pres- ented.First the personality of products is discussed.Products are divided into several categories to speed up the test generation.This strategy aims at generating a very compact test set for crosspoint defects through the fol- lowing steps:1)generate special test vectors for each category of products at the beginning of test generation. Each vector is capable of detecting a great amount of crosspoint defects;2)ge…
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    A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors
    Ashish Pancholy; Fidel Muradali; Vinod K.Agarwal;
    Journal of Computer Science and Technology, 1990, 5 (2): 175-186. 
    Abstract   PDF(514KB) ( 1151 )   Chinese Summary
    A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented.
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    Repairing VLSI/WSI Redundant Memories with Minimum Cost
    Huang Weikang; F.Lombardi;
    Journal of Computer Science and Technology, 1990, 5 (2): 187-196. 
    Abstract   PDF(477KB) ( 1159 )   Chinese Summary
    A new approach to repair memory chips with redundancy is proposed.This approach is based on the minimization of the repair cost.Algorithms for cost driven repair are presented.The algorithms can be ex- ecuted either on-line(concurrently with the testing of the memory),or off-line(at completion of testing). Analytical expressions for the repair cost under both circumstances are given.The presented algorithms are also perfect in the sense that they can correctly diagnose a repairable/unrepairable memory and f...
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    Testability Analysis at Switch Level for CMOS Circuits
    Shen Li;
    Journal of Computer Science and Technology, 1990, 5 (2): 197-202. 
    Abstract   PDF(144KB) ( 1146 )   Chinese Summary
    In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexity of the algorithm is nearly linear.
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    Orthogonal Algorithm of Logic Probability and Syndrome-Testable Analysis
    Zheng Chongxun; Zhang Kenong;
    Journal of Computer Science and Technology, 1990, 5 (2): 203-209. 
    Abstract   PDF(309KB) ( 1260 )   Chinese Summary
    A new method,orthogonal algorithm,is presented to compute the logic probabilities(i.e.signal probabili- ties)accurately.The transfer properties of logic probabilities are studied first,which are useful for the calcula- tion of logic probability of the circuit with random independent inputs.Then the orthogonal algorithm is des- cribed to compute the logic probability of Boolean function realized by a combinational circuit.This algorithm can make Boolean function“ORTHOGONAL”so that the logic probabilities can...
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ISSN 1000-9000(Print)

CN 11-2296/TP

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