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Volume 28 Issue 4
July  2013
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Abstract
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Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu, Bao-Xia Fan. A Robust and Power-Efficient SoC Implementation in 65nm[J]. Journal of Computer Science and Technology, 2013, 28(4): 682-688. DOI: 10.1007/s11390-013-1368-7
Citation: Bin Xiao, Yi-Fu Zhang, Yan-Ping Gao, Liang Yang, Dong-Mei Wu, Bao-Xia Fan. A Robust and Power-Efficient SoC Implementation in 65nm[J]. Journal of Computer Science and Technology, 2013, 28(4): 682-688. DOI: 10.1007/s11390-013-1368-7
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A Robust and Power-Efficient SoC Implementation in 65nm

  • 1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2. University of Chinese Academy of Sciences, Beijing 100049, China;
    3. Loongson Technology Corporation Limited, Beijing 100190, China

Funds: This work is supported by the National Natural Science Foundation of China under Grant Nos. 61003064, 61050002, 61070025, 61100163, the National High Technology Research and Development 863 Program of China under Grant Nos. 2012AA010901, 2012AA011002, 2012AA012202, 2013AA014301.
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  • Received Date: September 27, 2012
  • Revised Date: March 06, 2013
  • Published Date: July 04, 2013
    Abstract
  • Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.
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    • References (16)
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