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Volume 29 Issue 2
March  2014
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Peng Chen, Lei Zhang, Yin-He Han, Yun-Ji Chen. A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications[J]. Journal of Computer Science and Technology, 2014, 29(2): 239-246. DOI: 10.1007/s11390-014-1426-9
Citation: Peng Chen, Lei Zhang, Yin-He Han, Yun-Ji Chen. A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications[J]. Journal of Computer Science and Technology, 2014, 29(2): 239-246. DOI: 10.1007/s11390-014-1426-9
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A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications

  • 1 State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences Beijing 100190, China;
    2 University of Chinese Academy of Sciences, Beijing 100049, China

Funds: This paper is supported by the National Natural Science Foundation of China under Grant Nos. 601173006, 61221062, and the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No. XDA06010403.
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  • Author Bio:

    Peng Chen received his B.S. de-gree from the Department of Com-puter Science and Technology, Hefei University of Technology, in 2012. He is currently a master's student in the Institute of Computing Technol-ogy (ICT), Chinese Academy of Sci-ences (CAS), Beijing. His research interests include program analysis and accelerator design.

  • Received Date: October 29, 2013
  • Revised Date: January 02, 2014
  • Published Date: March 04, 2014
    Abstract
  • The combination of growing transistor counts and limited power budget within a silicon die leads to the utilization wall problem (a.k.a. "Dark Silicon"), that is only a small fraction of chip can run at full speed during a period of time. Designing accelerators for specific applications or algorithms is considered to be one of the most promising approaches to improving energy-effciency. However, most current design methods for accelerators are dedicated for certain applications or algorithms, which greatly constrains their applicability. In this paper, we propose a novel general-purpose many-accelerator architecture. Our contributions are two-fold. Firstly, we propose to cluster dataflow graphs (DFGs) of hotspot basic blocks (BBs) in applications. The DFG clusters are then used for accelerators design. This is because a DFG is the largest program unit which is not specific to a certain application. We analyze 17 benchmarks in SPEC CPU 2006, acquire over 300 DFGs hotspots by using LLVM compiler tool, and divide them into 15 clusters based on graph similarity. Secondly, we introduce a function instruction set architecture (FISC) and illustrate how DFG accelerators can be integrated with a processor core and how they can be used by applications. Our results show that the proposed DFG clustering and FISC design can speed up SPEC benchmarks 6.2X on average.
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