We use cookies to improve your experience with our site.

Indexed in:

SCIE, EI, Scopus, INSPEC, DBLP, CSCD, etc.

Submission System
(Author / Reviewer / Editor)
Advanced Search
Volume 31 Issue 1
January  2016
Turn off MathJax
Article Contents
Abstract
References
Ji-Liang Zhang, Qiang Wu, Yi-Peng Ding, Yong-Qiang Lv, Qiang Zhou, Zhi-Hua Xia, Xing-Ming Sun, Xing-Wei Wang. Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function[J]. Journal of Computer Science and Technology, 2016, 31(1): 124-136. DOI: 10.1007/s11390-016-1616-8
Citation: Ji-Liang Zhang, Qiang Wu, Yi-Peng Ding, Yong-Qiang Lv, Qiang Zhou, Zhi-Hua Xia, Xing-Ming Sun, Xing-Wei Wang. Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function[J]. Journal of Computer Science and Technology, 2016, 31(1): 124-136. DOI: 10.1007/s11390-016-1616-8
shu

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

  • 1 Software College, Northeastern University, Shenyang 110819, China;
    2 College of Information Science and Engineering, Hunan University, Changsha 410082, China;
    3 School of Physics and Electronics, Central South University, Changsha 410083, China;
    4 Research Institute of Information Technology, Tsinghua University, Beijing 100084, China;
    5 School of Computer and Software, Nanjing University of Information Science and Technology, Nanjing 210044, China

Funds: This work was supported in part by the National Science Foundation for Distinguished Young Scholars of China under Grant No. 61225012, the National Natural Science Foundation of China under Grant Nos. 61572123, 61501525, 61402162, 61232016, and U1405254, Hunan Province Science and Technology Project under Grant No. 2014RS4033, and the PAPD fund.
More Information
  • Author Bio:

    Ji-Liang Zhang received his B.E. degree from Shandong University of Science and Technology, Qingdao, in 2009, and his Ph.D. degree in computer science and technology from Hunan University, Changsha, in 2015. In 2013～2014, he worked as a research scholar at the Maryland Embedded Systems and Hardware Security Lab, University of Maryland, College Park. He is currently an associate professor in the Software College, Northeastern University, Shenyang. His research interests include hardware security, IOT security, embedded system security, and software security.

  • Corresponding author:

    Xing-Wei Wang E-mail: wangxw@mail.neu.edu.cn

  • Received Date: March 28, 2014
  • Revised Date: May 29, 2015
  • Published Date: January 04, 2016
    Abstract
  • Physical unclonable function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property (IP) protection, key generation and digital rights management. Ring oscillator (RO) PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires "hard macros" to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.
    • FullText(HTML)
    • References (35)
  • [1]
    Xia Z, Wang X, Sun X, Wang Q. A secure and dynamic multi-keyword ranked search scheme over encrypted cloud data. IEEE Transactions on Parallel and Distributed Systems. (to be appeared)
    [2]
    Ren Y, Shen J, Wang J, Han J, Lee S. Mutual verifiable provable data auditing in public cloud storage. Journal of Internet Technology, 2015, 16(2):317-323.
    [3]
    Zhang J, Qu G, Lv Y, Zhou Q. A survey on silicon PUFs and recent advances in ring oscillator PUFs. J. Comput. Sci. Technol., 2014, 29(4):664-678.
    [4]
    Suh G, Devadas S. Physical unclonable functions for device authentication and secret key generation. In Proc. the 44th DAC, June 2007, pp.9-14.
    [5]
    Zhang J, Lin Y, Lyu Y et al. FPGA IP protection by binding finite state machine to physical unclonable functions. In Proc. the 23rd International Conference on Field Programmable Logic and Applications (FPL), Sept. 2013.
    [6]
    Zhang J, Lin Y, Lyu Y, Qu G. A PUF-FSM binding scheme for FPGA IP protection and Pay-Per-Device licensing. IEEE Transactions on Information Forensics and Security, 2015, 10(6):1137-1150.
    [7]
    Lim D, Lee J, Gassend B, Suh G E, van Dijk M, Devadas S. Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. Syst., 2005, 13(10):1200- 1205.
    [8]
    Asim M, Guajardo J, Kumar S, Tuyls P. Physical Unclonable Functions and their applications to vehicle system security. In Proc. the 69th IEEE Vehicle Technology Conference, April 2009.
    [9]
    Alkabani Y, Koushanfar F. Active control and digital rights management of integrated circuit IP cores. In Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems, October 2008, pp. 227-234.
    [10]
    Koushanfar F. Provably secure active IC metering techniques for piracy avoidance and digital rights management. IEEE Trans. Inf. Forensics Secur., 2012, 7(1):51-63.
    [11]
    Zhang J, Wu Q, Chen J. Research on design method of dynamic partial reconfigurable system. Journal of Software Engineering, 2012, 6(2):21-30.
    [12]
    Anderson J H. A PUF design for secure FPGA-based embedded systems. In Proc. the 15th ASPDAC, Jan. 2010, pp.1-6.
    [13]
    Pappu R. Physical One-Way Functions. Massachusetts Ave, Cambridge, USA:MIT, 2001.
    [14]
    Maes R, Verbauwhede I. Physically unclonable functions:A study on the state of the art and future research directions. In Towards Hardware-Intrinsic Security, Information Security and Cryptography, Sadeghi A R, Naccache D (eds.), Springer-Verlag, 2010, pp.3-37.
    [15]
    Yin C, Qu G, Zhou Q. Design and implementation of a group-based RO PUF. In Proc. DATE, March 2013, pp.416- 421.
    [16]
    Maiti A, Schaumont P. Improved ring oscillator PUF:An FPGA friendly secure primitive. Journal of Cryptology, 2011, 4(2):375-397.
    [17]
    Morozov S, Maiti A, Schaumont P. An analysis of delay based PUF implementations on FPGA. In Proc. the 6th ARC, March 2010, pp.382-387.
    [18]
    Majzoobi M, Koushanfar F, Potkonjak M. Testing techniques for hardware security. In Proc. ITC, Oct. 2008.
    [19]
    Yu M D, Devadas S. Secure and robust error correction for physical unclonable functions. IEEE Design & Test of Computers, 2010, 27(1):48-65.
    [20]
    Majzoobi M, Koushanfar F, Potkonjak M. Techniques for design and implementation of secure reconfigurable PUFs. ACM Trans. Reconfigurable Technol. Syst., 2009, 2(1):5:1- 5:33.
    [21]
    Katzenbeisser S, Kocabas U, van der Leest V, Sadeghi A R, Schrijen G J, Wachsmann C. Recyclable PUFs:Logically reconfigurable PUFs. J. Cryptogr. Eng., 2011, 1(3):177-186.
    [22]
    Zhang J, Lin Y, Qu G. Reconfigurable binding against FPGA replay attacks. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015, 20(2):33:1-33:20.
    [23]
    Hammouri G, Dana A, Sunar B. CDs have fingerprints too. In Proc. the 11th CHES, Sept. 2009, pp.348-362.
    [24]
    Kumar S, Guajardo J, Maes R et al. The butterfly PUF:Protecting IP on every FPGA. In Proc. HOST, June 2008, pp.67-70.
    [25]
    Mills A, Vyas S, Patterson M et al. Design and evaluation of a delay-based FPGA physically unclonable function. In Proc. the 30th ICCD, Sept. 2012, pp.143-146.
    [26]
    Zhang J, Lin Y, Wu Q et al. Watermarking FPGA bitfile for intellectual property protection. Radioengineering, 2012, 21(2):764-771.
    [27]
    Kean T. Cryptographic rights management of FPGA intellectual property cores. In Proc. the ACM/SIGDA Symp. Field-Programmable Gate Arrays (FPGA), Feb. 2002, pp. 113-118.
    [28]
    Zhang J, Lin Y, Che W et al. Efficient verification of IP watermarks in FPGA designs through lookup table content extracting. IEICE Electronics Express, 2012, 9(22):1735- 1741.
    [29]
    Maes R, Schellekens D, Verbauwhede I. A pay-per-use licensing scheme for hardware IP cores in recent SRAMFPGAs. IEEE Transactions on Information Forensics and Security, 2012, 7(1):98-108.
    [30]
    Li J, Li X, Yang B, Sun X. Segmentation-based image copymove forgery detection scheme. IEEE Transactions on Information Forensics and Security, 2015, 10(3):507-518.
    [31]
    Xia Z, Wang X, Sun X, Liu Q, Xiong N. Steganalysis of LSB matching using differences between nonadjacent pixels. Multimedia Tools and Applications, 2014, DOI 10.1007/s11042-014-2381-8.
    [32]
    Xia Z, Wang X, Sun X, Wang B. Steganalysis of least significant bit matching using multi-order differences. Security and Communication Networks, 2014, 7(8):1283-1291.
    [33]
    Fu Z, Sun X, Liu Q, Zhou L, Shu J. Achieving efficient cloud search services:Multi-keyword ranked search over encrypted cloud data supporting parallel computing. IEICE Transactions on Communications, 2015, E98-B(1):190- 200.
    [34]
    Guo P, Wang J, Li B, Lee S. A variable threshold-value authentication architecture for wireless mesh networks. Journal of Internet Technology, 2014, 15(6):929-936.
    [35]
    Paral Z, Devadas S. Reliable and efficient PUF-based key generation using pattern matching. In Proc. the IEEE Int. Symp. Hardware-Oriented Security and Trust (HOST), May 2011, pp.128-133.
    • Relative Articles
  • Supplements (0)

Catalog

    Get Citation
    PDF
    XML
    Article views (75) PDF downloads (1413) Cited by()
    Related

    Copyright ©2025 JCST, All Rights Reserved     京ICP备05002829号-1

    Institute of Computing Technology, Chinese Academy of Sciences
    P.O. Box 2704, Beijing 100190, P.R. China

    Tel.: 86-10-62610746 E-mail: jcst@ict.ac.cn

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return